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SIP11204DLP-T1-E3

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
Document Number: 73868
S11-0975–Rev. C, 16-May-11
www.vishay.com
7
Vishay Siliconix
SiP11203, SiP11204
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
MOSFET RECTIFIER DRIVERS
Start-Up
At converter start-up, V
L
will typically be at or near 0 V.
Until such time as the UVLO
R
threshold is exceeded,
the main synchronous rectifier drivers are disabled, as
the supply voltage for the IC may be insufficient to
ensure that the output drivers will fully respond to input
commands. Without precautionary measures,
capacitive coupling between the drains and gates of
the synchronous rectifiers could cause spurious
conduction in the rectifiers. To prevent this, special
hold-off MOSFETs are switched in until the main
drivers are enabled. These internal hold-off
MOSFETs, which connect from OUTA to PGND and
OUTB to PGND, can typically conduct in excess of
400 mA with 1 V on OUTA or OUTB (Z
OUT
≅ 2.5 Ω).
Once V
L
rises above UVLO
R
, the main drivers are
enabled and the part assumes its normal mode of
operation, with pulses at INA being used to control
OUTA and pulses at INB being used to control OUTB.
Figure 3 and its related text provide additional details
on this topic.
Normal Operation
When enabled, the main driver outputs are non-
inverting with respect to the input signal. The drivers
are designed to provide the high peak currents
(2 - 4 A) required to rapidly charge and discharge the
gates of large synchronous rectifier MOSFETs, with a
greater turn-off (pull-down) current than turn-on
(pull-up) current, to prevent shoot-through in the
synchronous rectifiers.
Shut-Down
In the typical application circuit, cessation of primary
timing signals at INA and INB would cause both OUTA
and OUTB to be pulled high, which at the system level
would short-circuit of the converter output to ground
via the synchronous rectifiers. To avoid possible
negative effects of such an event, the SiP11203/
SiP11204 uses a missing-pulses detector to monitor
INA and INB and, if necessary, set the main output
drivers to a high-impedance state. At the same time
that the main drivers are disabled, a pull-down device
(current sink) of user-settable value is enabled on each
output, to gradually discharge OUTA and OUTB,
thereby performing a soft turn-off of the rectifier
MOSFETs. The pull-down current is set by the R
PD
resistor, and is given by the formula
I
PULL-DOWN
= 500 V/R
PD
. Such an event also causes
bypass capacitor at the the V
REF
pin to be discharged,
preparing the IC for a voltage-loop soft-start should the
primary resume sending timing signals. Further details
are given in the Applications Information section.
Synchronous Rectifier Phase-In
With a resistor connected between the R
DEL
pin and
ground, the SiP11203/SiP11204 will increase the low-
to-high propagation delay time from INA and INB to
OUTA and OUTB by an amount ΔT
DEL
. This interval
is proportional to the resistance used, and inversely
proportional to the voltage on V
REF
(ΔT
DEL
= k x R
DEL
/
V
REF
). As this delay occurs for high-going input
transitions only, it constitutes a hold-off time for the
synchronous rectifiers. As can be seen, ΔT
DEL
decreases as V
REF
ramps from a low level to its final
1.225 V level at start-up, or following any soft-start
event. If ΔT
DEL
is set to start at a sufficient value to
allow only diode-mode conduction in the rectifier
MOSFETs, the result will be a gentle transition from
diode-mode operation to fully synchronous
rectification, thereby avoiding a sudden change in the
average voltage drop seen at the output rectifiers.
Conventional operation can be achieved by tying the
R
DEL
pin to V
L
. The synchronous rectifier phase-in
function is explained in more detail in the Applications
Information section.
Output Over-voltage Protection: SiP11203 versus
SiP11204
For maximum flexibility in the way that the SiP11203/
SiP11204 parts react to an output over-voltage event,
the input to the over-voltage protect comparator
(OVP
IN
) is brought out separately from the error
amplifier inputs. Additionally, the outputs of the
SiP11203 and the SiP11204 respond differently to
an over-voltage: the SiP11203 is designed to rapidly
discharge an output bus that is experiencing an over-
voltage, while the SiP11204 is designed to avoid
sinking current from other supplies feeding the same
bus, relying instead upon system-level intervention to
provide complete load protection. The OVP
IN
function
is explained in more detail in the Applications
Information section.
www.vishay.com
8
Document Number: 73868
S11-0975–Rev. C, 16-May-11
Vishay Siliconix
SiP11203, SiP11204
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
APPLICATIONS INFORMATION
Powering SiP11203/SiP11204
The SiP11203/SiP11204 has an internal pre-regulator
to provide 5 V at V
L
, which biases many of the internal
sub-circuits. This allows the IC to operate from any
input voltage within the allowable V
IN
range. At the
same time, V
IN
provides the supply voltage to the gate
driver outputs (OUTA and OUTB) directly. The gate
drive level to the synchronous rectifier MOSFETs is
determined by V
IN
The V
IN
voltage can be derived using conventional
methods, such as an extra winding on the power
transformer or on the output inductor. Alternatively,
this supply can be derived from the pulse transformer
used to transmit synchronous rectifier timing signals
from the primary to the secondary, as shown in Figure
2 below. The voltage level on V
IN
will be determined by
the turn ratio of the pulse transformer and the
differential voltage between SRL of the Si9122,
Si9122A, Si9122E and SRH of of the Si9122, Si9122A,
Si9122E. Note that this circuit will cause the voltages
at INA and INB to be twice that of V
IN
. Therefore it may
be necessary to limit the voltage seen by INA and INB
in order to avoid exceeding their recommended
operating values.
START-UP DRIVER OPERATION
During start-up of the SiP11203/SiP11204, the
MOSFET drivers (OUTA and OUTB) are disabled until
V
L
is at 90 % of its final value. To fully prevent any
spurious turn-on of the synchronous rectifier
MOSFETs, the gates of the MOSFETs are held off
during this start up period. Until the main drivers are
enabled, the INA and INB drive paths are re-routed, or
“swapped,” inside the IC. In conjunction with a
dedicated n-channel hold-off MOSFET “inverter”
placed in parallel with each main driver, this allows the
IC to ground the appropriate synchronous rectifier gate
at the necessary time. See Figure 3.
If the first two pulses coming through the pulse
transformer are considered, the following sequence of
events follows:
• INA goes low, which would normally command the
OUTA driver to go low. This would prevent spurious
turn-on of the associated synchronous rectifier.
However, since the voltage to the IC is below its
normal operating level, it cannot be guaranteed that
OUTA can in fact go to its necessary state. For this
reason, the OUTA and OUTB drivers are disabled
while V
L
< UVLO
R
.
• When INA goes low, INB will be driven to a level of
2 x V
IN
. This is due to the way in which the
secondary of the pulse transformer is rectified to
provide V
IN
. Specifically, this results from the
rectifier diodes clamping the secondary’s negative
excursions one diode drop below ground (See
Figure 2).
Figure 2. Typical schematic showing how the V
IN
supply for SiP11203/SiP11204 is generated using the pulse transformer providing the
synchronous rectifier timing signals
SRH
SRL
INA
V
INB
GND
IN
SiP11203
SiP11204
SRH
SRL
INA
V
INB
GND
IN
SiP11203
SiP11204
SiP11203
SiP11204
Document Number: 73868
S11-0975–Rev. C, 16-May-11
www.vishay.com
9
Vishay Siliconix
SiP11203, SiP11204
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
• While V
L
is below the UVLO
R
threshold, the IC
“swaps” the synchronous rectifier drive paths. This
causes the high-going signal on INB to be applied
to the gate of an n-channel hold-off MOSFET,
which is in parallel with the main OUTA driver. This
MOSFET inverts the signal from INB, which causes
its drain to be pulled towards ground. This holds
OUTA low.
• During the deadtime in which neither INB nor INA is
driven high, the voltage on INA and that on INB will
be equal to the voltage on V
IN
. Depending upon the
exact value of V
IN
, this may or may not result in
both OUTA and OUTB being pulled low by their
associated inverter MOSFETs.
• During the next cycle of converter operation, all of
the above applies with the exception that INB is
now driven low, which will cause INA to be driven
high. This will in turn cause the hold-off MOSFET in
parallel with the main OUTB driver to conduct,
thereby holding OUTB low.
In this way, the SiP11203/SiP11204 “swap and invert”
function prevents any unwanted turn-on of the
synchronous rectifiers during start-up. Once V
L
reaches 90 % of its final value, the drive path inside the
IC is no longer swapped, and the inverting hold-off
MOSFETs are disabled.
FUNCTIONAL BLOCK DIAGRAM
START-UP DRIVER OPERATION
Assuming that V
IN
rises with suitable rapidity to a
voltage greater than 5.5 V, the factors controlling the
rate of rise of V
L
are the external V
L
bypass capacitor
value and the pre-regulator’s current limit. This gives
the following two equations:
• The time from start-up to
CUVLO
R
≅ (4.45 V/35 mA) x C
VL
, and
• The time from start-up to
UVLO
R
≅ (4.45 V/35 mA) x C
VL
.
Once V
L
has reached 90 % of its final value, the clamp
holding V
REF
at 0 V is released, allowing the voltage on
the V
REF
pin to rise at a rate set by the value of the
V
REF
capacitor. This gives the following equation:
• The time from UVLO
R
to V
REF
attaining a voltage of
1.1 V ≅
(1.1 V/410 µA) x C
VREF
.
These relationships are shown in Figure 4.
Figure 3. During converter startup, the synchronous MOSFET gate-driver outputs of the SiP11203/SiP11204 are reversed and inverted
to prevent spurious MOSFET switching
Hold-off
MOSFET
Hold-off
MOSFET
SW1 and SW2 are closed at start-up.
SW1 and SW2 open when V
L
> UVLO
R
.
SW1
SW2
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

SIP11204DLP-T1-E3

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Manufacturer:
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Description:
Switching Controllers Sec Sync Rect Ctrl w/Overvolt Protect
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