LTC4261/LTC4261-2
15
42612fd
For more information www.linear.com/LTC4261
10µA until the voltage at TMR reaches 2.56V. C
TMR
is then
quickly discharged with a 12mA current. The initial delay
expires when TMR is brought below 75mV. The duration
of the start-up delay is given by:
t
D
= 256ms •
C
TMR
1µF
If any of the above conditions is violated before the start-up
delay expires, C
TMR
is quickly discharged and the turn-on
sequence is restarted. After all the conditions are validated
throughout the start-up delay, the ON pin is then checked.
If it is high, the FET will be turned on. Otherwise, the FET
will be turned on when the ON pin is raised high or the FET
ON bit D3 in the CONTROL register is set to “1” through
the I
2
C interface.
The FET turn-on sequence follows by charging an external
capacitor at the SS pin (C
SS
) with a 10µA pull-up current
and the voltage at SS (V
SS
) is converted to a current
(I
GATE(UP)
) of 11.5µA· V
SS
/2.56V for GATE pull-up. When
the GATE reaches the FET threshold voltage, the inrush
current starts to flow through the FET and a current (I
RAMP
)
of 20µA· V
SS
/2.56V flows out of the RAMP pin and through
an external capacitor (C
R
) connected between RAMP and
V
OUT
. The SS voltage is clamped to 2.56V, which cor-
responds to I
GATE(UP)
= 11.5µA and I
RAMP
= 20µA. The
RAMP pin voltage is regulated at 1.1V and the ramp rate
of V
OUT
determines the inrush current:
I
INRUSH
= 20µA •
C
L
C
The ramp rate of V
SS
determines dI/dt of the inrush current:
INRUSH
dt
= 20µA •
L
C
•
256ms • C
If C
SS
is absent, an internal circuit pulls the SS pin from
0V to 2.56V in about 220µs.
When V
OUT
is ramped down to V
EE
, I
GATE
returns to
the GATE pin and pulls the GATE up to V
GATEH
. Figure 4
illustrates the start-up sequence of the LTC4261/
LTC4261
-2.
During board insertion and input power step, an internal
clamp turns on to hold the RAMP pin low. Capacitor C
F
and resistor R
F
suppress the noise at the RAMP pin. For
proper operation, R
F
• C
R
should not exceed 50µs. The
recommended value of C
F
is 3 • C
R
.
Power Good Monitors
When V
DS
of the pass transistor falls below 1.77V and
GATE pulls above V
Z
– 1.2V, an internal power good signal
is latched and a series of three delay cycles are started
as shown in Figure 4. When the first delay cycle with a
duration of 2t
D
expires, the PG pin pulls low as a power
good signal to turn on the first module. When the second
delay cycle (2t
D
) expires, the PGIO pin pulls low as a power
good signal to turn on the second module. The third delay
cycle with a duration of 4t
D
is for PGI check. Before the
third delay cycle expires, the PGI pin must be pulled low
by an external supply monitor (such as the LTC2900 in
Figure 2) to keep the FET on. Otherwise, the FET is turned
off and the power bad fault (PBAD) is logged in the FAULT
register. The 2t
D
timer delay is obtained by charging C
TMR
with a 5µA current and discharging C
TMR
with a 12mA
current when TMR reaches 2.56V. For the 4t
D
timer delay,
the charging and discharging currents of C
TMR
are both
5µA. The power good signals at PG and PGIO are reset in
all FET turn-off conditions except the overvoltage fault.
Turn-Off Sequence and Auto-Retry
In any of the following conditions, the FET is turned off
by pulling down GATE with a 110mA current, and C
SS
and C
TMR
are discharged with 12mA currents.
1. The ON pin is low or the ON bit in the CONTROL reg-
ister is set to 0.
2. The EN
pin is high.
3. The voltage at UVL is lower than 2.291V and the volt
-
age at UVH is lower than 2.56V (undervoltage fault).
4. The voltage at OV is higher than 1.77V (overvoltage
fault).
5. The voltage at V
IN
is lower than 9V (V
IN
undervoltage
lockout).
APPLICATIONS INFORMATION
