LTC4261CGN#PBF Datasheet LTC4261IGN#PBF, LTC4261CGN#PBF, LTC4261IGN-2#PBF | P25-P27

LTC4261/LTC4261-2

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START and STOP Conditions

When the bus is idle, both SCL and SDA must be high. A

bus master signals the beginning of a transmission with

a START condition by transiting SDA from high to low

while SCL is high. When the master has ﬁnished com

municating with the slave, it issues a STOP condition by

transiting

SDA

from low to high while SCL is high. The

bus is then free for another transmission.

Stuck-Bus Reset

The LTC4261/LTC4261-2 I

C interface features a stuck-

bus reset timer. The low conditions of the SCL and the

SDAI pins are ORed to start the timer. The timer is reset

when both SCL and SDAI are pulled high. If the SCL pin

or the SDAI pin is held low for over 66ms, the stuck-bus

timer will expire and the internal I

C state machine will

be reset to allow normal communication after the stuck-

low condition is cleared. When the SCL pin and the SDAI

pin are held low alternatively, if the ORed low period of

SCL and SDAI exceeds 66ms before the timer reset con

dition (both SCL and SDAI are high) occurs, the stuck-

bus timer will expire and the I

C state machine is reset.

C Device Addressing

Any of eight distinct I

C bus addresses are selectable us-

ing the three-state pins ADR0 and ADR1, as shown in

Table

1. Note that the conﬁguration of ADR0 = L and ADR1

= H is used to enable the single-wire broadcasting mode.

For the eight I

C bus addresses, address bits B6, B5 and

B4 are conﬁgured to (001) and the least signiﬁcant bit B0

is the R/W bit. In addition, the LTC4261/LTC4261-2 will

respond to two special addresses. Address (0011 111)

is a mass write used to write to all LTC4261/LTC4261-2s,

regardless of their individual address settings. Address

(0001 100) is the SMBus Alert Response Address. If the

LTC4261/LTC4261-2 are pulling low on the ALERT pin,

it will acknowledge this address using the SMBus Alert

Response Protocol.

Acknowledge

The acknowledge signal is used for handshaking be

tween the transmitter and the receiver to indicate that the

last byte of data was received. The transmitter always re-

leases the SDA line during the acknowledge clock pulse.

When the slave is the receiver, it must pull down the SDA

line so that it remains LOW during this pulse to acknowl

edge receipt of the data. If the slave fails to acknowl-

edge by leaving SDA HIGH, then the master can abort

the transmission by generating a STOP condition. When

the master is receiving data from the slave, the master

must pull down the SDA line during the clock pulse to

indicate receipt of the data. After the last byte has been

received the master will leave the SDA line HIGH (not

acknowledge) and issue a STOP condition to terminate

the transmission.

Write Protocol

The master begins communication with a STAR

T con

dition followed by the seven bit slave address and the

R/W bit set to zero. The addressed LTC4261/L

TC4261-2

acknowledge this and then the master sends a command

byte which indicates which internal register the master

wishes to write. The LTC4261/LTC4261-2 acknowledge

this and then latch the lower four bits of the command

byte into its internal Register Address pointer. The master

then delivers the data byte and the LTC4261/LTC4261-2

acknowledge once more and latch the data into its inter

nal register. The transmission is ended when the master

sends a STOP condition. If the master continues sending

a second data byte, as in a Write Word command, the

second data byte will be acknowledged by the LTC4261/

LTC4261-2 but ignored.

Read Protocol

The master begins a read operation with a START con

dition followed by the seven bit slave address and the

R/W bit set to zero. The addressed LTC4261/L

TC4261-2

acknowledge this and then the master sends a command

byte that indicates which internal register the master

wishes to read. The LTC4261/LTC4261-2 acknowledge

this and then latch the lower four bits of the command

byte into its internal Register Address pointer. The mas

ter then sends a repeated START condition followed by

the same seven bit address with the R/W

bit now set to

one. The LTC4261/LTC4261-2 acknowledge and send the

contents of the requested register. The transmission is

ended when the master sends a STOP condition. If the

APPLICATIONS INFORMATION

LTC4261/LTC4261-2

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master acknowledges the transmitted data byte, as in a

Read Word command, the LTC4261/LTC4261-2 will re-

peat the requested register as the second data byte. Note

that the Register Address pointer is not cleared at the

end of the transaction. Thus the Receive Byte protocol

can be used to repeatedly read a speciﬁc register

Alert Response Protocol

The L

TC4261/LTC4261-2 implement the SMBus Alert

Response Protocol as shown in Figure 16. If enabled

to do so through the ALERT register C, the LTC4261/

LTC4261-2 will respond to faults by pulling the ALERT

pin low. Multiple LTC4261/LTC4261-2s can share a com

mon ALERT line and the protocol allows a master to de-

termine which L

TC4261/LTC4261-2s are pulling the line

low. The master begins by sending a ST

ART bit followed

by the special Alert Response Address (0001 100)b with

the R/W bit set to one. Any LTC4261/LTC4261-2 that is

pulling its ALERT pin low will acknowledge and begin

sending back its individual slave address.

Figure 16. LTC4261 Serial Bus SDA Alert Response Protocol

APPLICATIONS INFORMATION

this means repeated or continuing faults will not gener-

ate alerts until the associated FAULT register bit has been

cleared.

Single-Wire Broadcast Mode

The L

TC4261/LTC4261-2 provides a single-wire broadcast

mode in which selected register data are sent out to the

SDAO pin without clocking the SCL line (Figure 17). The

single-wire broadcast mode is enabled by setting the

ADR1 pin high and the ADR0 pin low (the I

C interface is

disabled). At the end of each conversion of the three ADC

channels, a stream of eighteen bits are broadcasted to

SDAO with a serial data rate of 15.3kHz ±20% in a format

as illustrated in Figure 18. The data bits are encoded with

an internal clock in a way similar to Manchester encoding

that can be easily decoded by a microcontroller or FPGA.

Each data bit consists of a noninverting phase and an

inverting phase. During the conversion of each ADC chan

nel, SDAO is idle at high. At the end of the conversion, the

SDAO pulls low. The START bit indicates the beginning of

data broadcasting and is used along with the dummy bit

(DMY) to measure the internal clock cycle (i.e., the serial

data rate). Following the DMY bit are two channel code

bits CH1 and CH0 labeling the ADC channel (see Table

10). Ten data bits of the ADC channel (ADC9-0) and three

FAULT register bits (B2, B1 and B0) are then sent out. A

parity bit (PRTY) ends each data stream. After that the

SDAO line enters the idle mode with SDAO pulled high.

The following data reception procedure is recommended:

0. Wait for INTV

rising edge.

1. Wait for SDAO falling edge.

2. The first falling edge could be a glitch, so check again

after a delay of 10µs. If back to high, wait again. If still

low, it is the START bit.

3. Use the following low-to-high and high-to-low transis

tions to measure 1/2 of the internal clock cycle.

ALERT

RESPONSE

ADDRESS

0 0 0 1 1 0 0

DEVICE

ADDRESS

0 0 1 a3:a0 0 11

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A A

An arbitration scheme ensures that the LTC4261/

LTC4261-2 with the lowest address will have priority;

all others will abort their response. The successful re

sponder will then release its ALERT pin while any others

will continue to hold their ALERT pins low. Polling may

also be used to search for any LTC4261/LTC4261-2 that

have detected faults. Any LTC4261/LTC4261-2 pulling its

ALERT pin low will also release it if it is individually ad

dressed during a read or write transaction.

The ALER

signal will not be pulled low again until the

FAULT register indicates a different fault has occurred or

the original fault is cleared and it occurs again. Note that

LTC4261/LTC4261-2

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Figure 17. Single-Wire Broadcast Mode

Figure 18. Single-Wire Broadcast Data Format

4. Wait for the second low-to-high transistion (middle of

DMY bit).

5. Wait 3/4 of a clock cycle.

6. Sample bit CH1, wait for transistion.

7. Wait 3/4 of a clock cycle.

8. Sample bit CH0, wait for transistion.

9. Wait 3/4 of a clock cycle.

10. Sample ADC9, wait for transistion.

11. Continue until all bits are read.

APPLICATIONS INFORMATION

The above procedure can be ported to a microcontroller

or used to design a state machine in FPGA. Code should

have timeouts in case an edge is missed. Abort the read

if it takes more than double the typical time (1.2ms) for

all 18 bits to be clocked out.

A typical application circuit with the LTC4261/LTC4261-2

in the broadcast mode is illustrated in Figure 19, where

input voltage, V

of the FET and V

SENSE

are monitored.

The register addresses and contents are summerized in

Table 1 and Table 2. The function of each register bit is

detailed in Tables 3 to 9.

SDAI

SCL

SDAO

ADR1

ADR0

LTC4261

INTV

6 × 0.51k IN SERIES

1/4W EACH

–48V RTN

–48V INPUT

0.1µF

1µF

7.5k

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GND

ANODE

CATHODE

HCPL-0300

OUT

MICRO-

CONTROLLER

INTERNAL

CLK

DATA

SDAO

START

START DMY CH1 CH0 OC OV PRTY

4261 F18

UVADC9

.. .. ..

ADC0

CH1

CH0

ADC9

ADC0

ADC9

ADC0

PRTY

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LTC4261CGN#PBF

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LTC4261CGN#PBF

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