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LTC4261CGN#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34
LTC4261/LTC4261-2
22
42612fd
For more information www.linear.com/LTC4261
Ejector Switch or Loop-Through Connection Sense.
Floating switch contacts or a connection sense loop also
work well with the ON pin, replacing the phototransistor
in Figure 9a. If an insertion debounce delay is desired,
use the EN pin as shown in Figure 9c. Like Figures 9a
and 9b, this circuit works on either side of the backplane
connector.
Short Pin to RTN. Figure 9d uses the UV divider string to
detect board insertion. This method works equally well in
both backplane and board resident applications.
AdvancedTCA Style Control. Figure 2 shows an ATCA
application using EN as the interface to the LTC4261.
Register bit A4 allows the I
2
C port to monitor the status
of EN and by setting C4 high, bit B4 can generate an alert
to instantly report any changes in the state of EN.
I
2
C Only Control. To lock out EN and ON, use the con-
figuration shown in Figure 9e and control the GATE pin
with register bit D3. The circuit defaults off at power up.
T
o default on, connect the ON pin to INTV
CC
. Either FLTIN
or PGIO can be used as an input to monitor a connection
sense or other control signal. PGIO is configured as an
input by setting register bits D6 and D7 high; its input
state is stored at location B6. FLTIN is always an input
whose state is available from register bit B7. FLTIN gen
-
erates an alert if C7 is set high.
Data Converter
The LTC4261/LTC4261-2 incorporates a 10-bit DΣ ana-
log-to-digital converter (ADC) that continuously moni-
tors three different voltages at (in the sequence of)
SENSE, ADIN2/OV (SSOP/QFN) and ADIN. The
DΣ ar-
chitecture inherently averages signal noise during the
measurement period. The
voltage
between the SENSE
pin and V
EE
is monitored with a 64mV full scale and
62.5µV resolution, and the data is stored in registers E
and F. The ADIN and the ADIN2/OV pins are monitored
with a 2.56V full scale and 2.5mV resolution. The data
for the ADIN2/OV pin is stored in registers G and H. The
data for the ADIN pin is stored in registers I and J.
The results in registers E, F, G, H, I and J are updated at
a frequency of 7.3Hz. Setting CONTROL register bit D5
invokes a test mode that halts updating of these registers
so that they can be written to and read from for software
testing. By invoking the test mode right before reading
the ADC data registers, the 10-bit data separated in two
registers are synchronized.
The ADIN and ADIN2 pins can be used to monitor input
and output voltages of the Hot Swap controller as shown
in Figures 1 and 2.
Figure 9. On/Off Control of the LTC4261
APPLICATIONS INFORMATION
INTV
CC
LTC4261
(9a) Opto-Isolator Control
5V
ON
47k
1k
EN
–48V
V
EE
INTV
CC
LTC4261
(9c) Contact Debounce Delay Upon
Insertion for Use with an Ejector
Switch or Loop-Through Style
Connection Sense
EN
100k
LOOP OR
SWITCH
10nF
1M
ON
–48V
V
EE
INTV
CC
LTC4261
(9b) Logic Control
ON EN
–48V
V
EE
INTV
CC
I
2
C
42612 F09
LTC4261
(9e) I
2
C-Only Control
ON
EN
SDAO
SDAI
SCL
DEFAULT
ON
DEFAULT
OFF
–48V
V
EE
INTV
CC
LTC4261
(9d) Short Pin Connection Sense to RTN
ON
EN
UVL
UVH
28.7k
–48V
INPUT
–48V
RTN
V
EE
453k
LTC4261/LTC4261-2
23
42612fd
For more information www.linear.com/LTC4261
Configuring the PGIO Pin
Table 6 describes the possible states of the PGIO pin us-
ing the CONTROL register bits D6 and D7. At power-up
the default state is for the PGIO pin to pull low when
the second power good signal is ready
. Other uses for
the PGIO pin are to go high impedence when the sec
-
ond power good is ready
, a general purpose output and a
general purpose input. When the PGIO pin is configured
as a general purpose output, the status of bit C6 is sent
out to the pin. When it is configured as a general pur
-
pose input, if the input voltage at PGIO is higher than
1.25V
, both bit A6 in the ST
ATUS register and bit B6 in
the FAULT register are set. If the input voltage at PGIO
subsequently drops below 1.25V, bit A6 is cleared. Bit
B6 can be cleared by resetting the FAULT register as de
-
scribed previously.
Design Example
As a design example, consider the 200W application with
C
L
= 330µF as shown in Figure 1. The operating voltage
range is from 43V to 71V with a UV turn-off threshold of
38.5V.
The design flow starts with calculating the maximum in
-
put current:
I
MAX
=
200W
36V
= 5.6A
where 36V is the minimum input voltage.
The selection of the sense resistor, R
S
, is determined by
the minimum current limit threshold and maximum input
current:
R
S
=
DV
SENSE(MIN)
I
MAX
=
45mV
5.6A
= 8mW
The inrush current is set to 0.66A using C
R
:
C
R
= C
L
•
I
RAMP
I
INRUSH
= 330µF •
20µA
0.66A
= 10nF
The value of R
F
and C
F
are chosen to 1k and 33nF as
discussed previously.
The FET is selected to handle the maximum power dissi-
pation during start-up or an input step. The latter usually
results in a larger power due to summation of the inrush
current charging C
L
and the load current. For a 36V input
step, the total P
2
t in the FET is approximated by:
P
2
t = 36V •I
MAX
( )
2
•
t
3
where t is the time it takes to charge up C
L
:
t =
C
L
• 36V
I
INRUSH
=
330µF • 36V
0.66A
= 18m
s
which gives a P
2
t value of 244W
2
s.
Now the P
2
t given by the SOA (safe operating area)
curves of candidate FETs must be higher than 244W
2
s.
The SOA curves of the IRF1310NS provide for 5A at 50V
(250W) for 10ms, which gives a P
2
t value of 625W
2
s and
satisfies the requirement.
Sizing R1, R2 and R3 for the required UV and OV thresh
-
old voltages:
V
UV(RISING)
= 43V, V
UV(FALLING)
= 38.5V, (using
V
UVH(TH)
= 2.56V and V
UVH(TH)
= 2.291V)
V
OV(RISING)
= 72.3V, V
OV(FALLING)
= 70.7V (using
V
OV(TH)
= 1.77V rising and 1.7325V falling)
Layout Considerations
To achieve accurate current sensing, a Kelvin connection
is recommended (Figure 10). The minimum trace width
for 1oz copper foil is 0.02" per amp to make sure the
trace stays at a reasonable temperature. Using 0.03" per
amp or wider is recommended. Note that 1oz copper ex
-
hibits a sheet resistance of about 530µW/square. Small
resistances add up quickly in high current applications.
The V
EE
pin of the LTC4261 should be connected to a
separate plane that is different from the main –48V in-
put plane. To improve noise immunity, as shown in
Figure
10, the V
EE
connections of all capacitors, resistive
dividers, opto-isolators and I
2
C common must be made
directly to the local V
EE
plane, not the –48V input plane.
APPLICATIONS INFORMATION
LTC4261/LTC4261-2
24
42612fd
For more information www.linear.com/LTC4261
I
2
C Interface
The LTC4261/LTC4261-2 feature an I
2
C interface to pro-
vide access to the ADC data registers and four other regis-
ters for monitoring and control of the pass FET. Figure
11
shows a general data transfer format using the I
2
C. The
LTC4261/LTC4261-2 are read-write slave devices and
support SMBus bus Read Byte, Write Byte, Read Word and
Write Word commands. The second word in a Read Word
command will be identical to the first word. The second
word in a Write Word command is ignored. The data for
-
mats for these commands are shown in Figures 12 to 15.
Using Opto-Isolators with SDA
The LTC4261/LTC4261-2 split the SDA line into SDAI (in
-
put) and SDAO (output) for convenience of opto-coupling
with the host. If opto-isolators are not used then tie SDAI
and SDAO together to form a normal SDA line. When us
-
ing opto-isolators, connect the SDAI pin to the output of
the incoming opto-isolator and connect the SDAO pin to
the input of the outgoing opto-isolator (see Figure 2). If
the SDAI and SDAO on the master controller are not tied
together, the ACK bit of SDAO must be returned back to
SDAI. If the ALERT line is used as an interrupt for the
host to respond to a fault in real time, connect the ALERT
pin to an opto-isolator in a way similar to that for the
SDAO pin as shown in Figure 2.
Figure 11. Data Transfer over I
2
C or SMBus
Figure 12. LTC4261 Serial Bus SDA Write Byte Protocol
Figure 13. LTC4261 Serial Bus SDA Write Word Protocol
Figure 14. LTC4261 Serial Bus SDA Read Byte Protocol
Figure 15. LTC4261 Serial Bus SDA Read Word Protocol
APPLICATIONS INFORMATION
SCL
SDA
START
CONDITION
STOP
CONDITION
ADDRESS R/W ACK DATA ACK DATA ACK
1 - 7 8 9
42612 F11
a6 - a0 b7 - b0 b7 - b0
1 - 7 8 9 1 - 7 8 9
P
S
S ADDRESS
0 0 1 a3:a0
42612 F12
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
A: ACKNOWLEDGE (LOW)
A
: NOT ACKNOWLEDGE (HIGH)
R: READ BIT (HIGH)
W: WRITE BIT (LOW)
S: START CONDITION
P: STOP CONDITION
COMMAND DATA
X X X X b3:b00
W
0 0 0b7:b0
A A A P
S ADDRESS
0 0 1 a3:a0
COMMAND DATA DATA
X X X X b3:b00
W
0 0 0 0
42612 F13
X X X X X X X Xb7:b0
A
A A A P
S ADDRESS
0 0 1 a3:a0 0 0 1 a3:a0 1 0
COMMAND S ADDRESS R A
b7:b0 1
DATA
X X X X b3:b00
W
0 0
42612 F14
A A A P
S ADDRESS
0 0 1 a3:a0 0 0 1 a3:a0 1 0
COMMAND S ADDRESS R A
b7:b0 1
DATA
X X X X b3:b00
W
0 0
42612 F15
A
0
A
b7:b0
DATA
A A P
MOSFET
TO SENSE PIN
–48V INPUT PLANE
V
EE
PLANE
LTC4261 V
EE
PIN
ALL CAPACITORS
ALL RESISTIVE DIVIDERS
ALL OPTO-ISOLATORS
I
2
C COMMON
D
G
S
R
S
VIAS
42612 F10
•
•
•
•
Figure 10. Layout Example of V
EE
Plane, –48V Input Plane and
Sense Resistor Connection
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LTC4261CGN#PBF

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Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers Neg V Hot Swap Cntrs w/ ADC & I2C Mon in
Lifecycle:
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