LTC4261/LTC4261-2
17
42612fd
For more information www.linear.com/LTC4261
EN and ON
Figure 5 shows a logic diagram for EN and ON as they
relate to GATE, ALERT and internal registers A4, A7, B4,
C4 and D3. Also affecting GATE is the status of UV, OV
and several other fault conditions. The EN and ON pins
have 0.8V to 2V logic thresholds relative to V
EE
with a
maximum input leakage current of ±2µA.
Register bit A4 indicates the present state of EN, and B4
is set high whenever EN changes state. Rising and falling
edges at the ON pin set and clear FET-on control bit, D3.
Another path allows a falling edge at EN to latch a high
state at the ON pin (such as when ON is permanently
pulled high) into D3 after a time delay. Both B4 and D3
can be set or cleared directly by I
2
C, and both are cleared
low whenever INTV
CC
drops below its UVLO threshold.
The condition of the GATE pin output is controlled by
register bit A7, which is the AND of A4, D3 and the ab
-
sence of UV, OV and other faults.
Overcurrent Protection and Overcurrent Fault
The LTC4261/LTC4261-2 feature two levels of protec
-
tion from short-circuit and overcurrent conditions. Load
current is monitored by the SENSE pin and resistor
R
S
. There are two distinct thresholds for the voltage at
SENSE: 50mV for engaging the active current limit loop
and starting a 530µs circuit breaker timer and 250mV for
a fast GATE pull-down to limit peak current in the event
of a catastrophic short circuit or an input step.
In an overcurrent condition, when the voltage drop across
R
S
exceeds 50mV, the current limit loop is engaged and
an internal 530µs circuit breaker timer is started. The
current limit loop servos the GATE to maintain a constant
output current of 50mV/R
S
. When the circuit breaker
timer expires, the FET is turned off by pulling GATE down
with a 110mA current, the capacitors at SS and TMR are
discharged and the power good signals are reset. At this
time, the overcurrent present bit A2 and the overcurrent
fault bit B2 are set, and the circuit breaker timer is reset.
After the FET is turned off, the overcurrent present bit
A2 is cleared. If the overcurrent auto-retry bit D2 has
been set, the FET will turn on again automatically after
a cooling time of 4t
D
. Otherwise, the FET will remain off
until the overcurrent fault bit B2 is reset. When the over-
current fault bit is reset (see Resetting Faults), the FET
is allowed to turn on again after a delay of 4t
D
. The 4t
D
cooling time associated with the overcurrent fault will not
be interrupted by any other fault condition. See Figure 6
for operation of LTC4261/LTC4261-2 under overcurrent
condition followed by auto-retry.
Figure 5. Logic Block Diagram of EN and ON Pins
APPLICATIONS INFORMATION
R/W
I
2
C
CLR
Q
S
R
R/W
CLR
INTV
CC
UVLO
INTV
UVLO
ABSENCE OF UV/OV AND OTHER FAULTS
Q
S
CLR
Q
S
1 t
D
TIMER
DELAY
EDGE
DETECTOR
STATE-CHANGE
DETECTOR
EN
B4
C4
ALERT*
GATE ON
ALERT
42612 F05
READ ANY REGISTER
*B4 •C4 IS ONE OF SEVEN CONDITIONS
THAT CAN GENERATE AN ALERT OUTPUT.
SEE TABLE 5
I
2
C ALERT RESPONSE
A4 A7
D3
