13 of 30 May 10, 2016
IDT 89HPES10T4G2 Data Sheet
Figure 5 JTAG AC Timing Waveform
Signal Symbol
Reference
Edge
Min Max Unit
Timing
Diagram
Reference
JTAG
JTAG_TCK Tper_16a none 50.0 ns See Figure 5.
Thigh_16a,
Tlow_16a
10.0 25.0 ns
JTAG_TMS
1
,
JTAG_TDI
1.
The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
Tsu_16b JTAG_TCK rising 2.4 ns
Thld_16b 1.0 ns
JTAG_TDO Tdo_16c JTAG_TCK falling 20 ns
Tdz_16c
2
2.
The values for this symbol were determined by calculation, not by testing.
—20ns
JTAG_TRST_N Tpw_16d
2
none 25.0 ns
Table 12 JTAG AC Timing Characteristics
Tpw_16d
Tdz_16cTdo_16c
Thld_16b
Tsu_16b
Thld_16b
Tsu_16b
Tlow_16aTlow_16a
Tper_16a
Thigh_16a
JTAG_TCK
JTAG_TDI
JTAG_TMS
JTAG_TDO
JTAG_TRST_N
14 of 30 May 10, 2016
IDT 89HPES10T4G2 Data Sheet
Recommended Operating Supply Voltages
Absolute Maximum Voltage Rating
Warning: For proper and reliable operation in adherence with this data sheet, the device should not exceed the recommended operating voltages
in Table 13. The absolute maximum operating voltages in Table 14 are offered to provide guidelines for voltage excursions outside the recommended
voltage ranges. Device functionality is not guaranteed at these conditions and sustained operation at these values or any exposure to voltages outside
the maximum range may adversely affect device functionality and reliability.
Power-Up/Power-Down Sequence
During power supply ramp-up, V
DD
CORE must remain at least 1.0V below V
DD
I/O at all times. There are no other power-up sequence require-
ments for the various operating supply voltages.
The power-down sequence can occur in any order.
Recommended Operating Temperature
Symbol Parameter Minimum Typical Maximum Unit
V
DD
CORE Internal logic supply 0.9 1.0 1.1 V
V
DD
I/O I/O supply except for SerDes LVPECL/CML 3.135 3.3 3.465 V
V
DD
PEA
1
1.
V
DD
PEA and V
DD
PETA should have no more than 25mV
peak-peak
AC power supply noise superimposed on the 1.0V nominal DC
value.
PCI Express Analog Power 0.95 1.0 1.1 V
V
DD
PEHA
2
2.
V
DD
PEHA should have no more than 50mV
peak-peak
AC power supply noise superimposed on the 2.5V nominal DC value.
PCI Express Analog High Power 2.25 2.5 2.75 V
V
DD
PETA
1
PCI Express Transmitter Analog Voltage 0.95 1.0 1.1 V
V
SS
Common ground 0 0 0 V
Table 13 PES10T4G2 Operating Voltages
Core Supply
PCIe Analog
Supply
PCIe Analog
High Supply
PCIe
Transmitter
Supply
I/O Supply
1.5V 1.5V 4.6V 1.5V 4.6V
Table 14 PES10T4G2 Absolute Maximum Voltage Rating
Grade Temperature
Commercial 0
C to +70C Ambient
Industrial -40
C to +85C Ambient
Table 15 PES10T4G2 Operating Temperatures
15 of 30 May 10, 2016
IDT 89HPES10T4G2 Data Sheet
Power Consumption
Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13
(and also listed below).
Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in
Table 13 (and also listed below).
Thermal Considerations
This section describes thermal considerations for the PES10T4G2 (19mm
2
CABGA324 package). The data in Table 17 below contains information
that is relevant to the thermal performance of the PES10T4G2 switch.
Note: It is important for the reliability of this device in any user environment that the junction temperature not exceed the T
J(max)
value
specified in Table 17. Consequently, the effective junction to ambient thermal resistance (
JA
) for the worst case scenario must be
maintained below the value determined by the formula:
JA
= (T
J(max)
- T
A(max)
)/P
Given that the values of T
J(max)
, T
A(max)
, and P are known, the value of desired
JA
becomes a known entity to the system designer. How to
achieve the desired
JA
is left up to the board or system designer, but in general, it can be achieved by adding the effects of
JC
(value
provided in Table 17), thermal resistance of the chosen adhesive (
CS
), that of the heat sink (
SA
), amount of airflow, and properties of the
circuit board (number of layers and size of the board). As a general guideline, this device will not need a heat sink if the board has 8 or more
layers AND the board size is larger than 4"x12" AND airflow in excess of 0.5 m/s is available. It is strongly recommended that users perform
their own thermal analysis for their own board and system design scenarios.
Number of active
Lanes per Port
Core Supply
PCIe Analog
Supply
PCIe Analog
High Supply
PCIe Termin-
ation Supply
I/O Supply Total
Typ
1.0V
Max
1.1V
Typ
1.0V
Max
1.1V
Typ
2.5V
Max
2.75V
Typ
1.0V
Max
1.1V
Typ
3.3V
Max
3.465V
Typ
Power
Max
Power
4/2/2/2
(Full swing)
mA 531 781 402 484 194 275 207 238 3 4
Watts 0.53 0.86 0.40 0.53 0.49 0.76 0.21 0.26 0.01 0.02 1.64 2.43
2/2/2/2
(Full swing)
mA 440 550 320 352 138 165 108 117 3 4
Watts 0.44 0.61 0.32 0.39 0.25 0.45 0.11 0.13 .01 .02 1.23 1.6
Table 16 PES10T4G2 Power Consumption
Symbol Parameter Value Units Conditions
T
J(max)
Junction Temperature 125
o
CMaximum
T
A(max)
Ambient Temperature 70
o
CMaximum
JA(effective)
Effective Thermal Resistance, Junction-to-Ambient
23.6
o
C/W Zero air flow
16.8
o
C/W 1 m/S air flow
15.4
o
C/W 2 m/S air flow
JB
Thermal Resistance, Junction-to-Board 14.5
o
C/W
JC
Thermal Resistance, Junction-to-Case 7.6
o
C/W
P Power Dissipation of the Device 2.43 Watts Maximum
Table 17 Thermal Specifications for PES10T4G2, 19x19 mm CABGA324 Package

89HPES10T4G2ZBBCG8

Mfr. #:
Manufacturer:
IDT
Description:
PCI Interface IC PCI EXPRESS SWITCH
Lifecycle:
New from this manufacturer.
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