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89HPES10T4G2ZBBCG8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
4 of 30 May 10, 2016
IDT 89HPES10T4G2 Data Sheet
Pin Description
The following tables list the functions of the pins provided on the PES10T4G2. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Note: In the PES10T4G2, the three downstream ports are labeled ports 2, 4, and 6.
Signal Type Name/Description
PE0RN[3:0]
PE0RP[3:0]
I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0. Port 0 is the upstream port.
PE0TN[3:0]
PE0TP[3:0]
O PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 0. Port 0 is the upstream port.
PE2RN[1:0]
PE2RP[1:0]
I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pairs for port 2.
PE2TN[1:0]
PE2TP[1:0]
O PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 2.
PE4RN[1:0]
PE4RP[1:0]
I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pairs for port 4.
PE4TN[1:0]
PE4TP[1:0]
O PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 4.
PE6RN[1:0]
PE6RP[1:0]
I PCI Express Port 6 Serial Data Receive. Differential PCI Express receive
pairs for port 6.
PE6TN[1:0]
PE6TP[1:0]
O PCI Express Port 6 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 6.
PEREFCLKP[0]
PEREFCLKN[0]
I PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
REFCLKM I PCI Express Reference Clock Mode Select. This signal selects the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
This pin should be static and not change following the negation of
PERSTN.
Table 2 PCI Express Interface Pins
Signal Type Name/Description
MSMBADDR[4:1] I Master SMBus Address. These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus.
MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas-
ter SMBus.
Table 3 SMBus Interface Pins (Part 1 of 2)
5 of 30 May 10, 2016
IDT 89HPES10T4G2 Data Sheet
SSMBADDR[5,3:1] I Slave SMBus Address. These pins determine the SMBus address to
which the slave SMBus interface responds.
SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans-
fers on the slave SMBus.
SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave
SMBus.
Signal Type Name/Description
GPIO[0] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P2RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 2.
GPIO[1] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P4RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 4.
GPIO[2] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN0
Alternate function pin type: Input
Alternate function: I/O expander interrupt 0 input.
GPIO[3] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[4] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN2
Alternate function pin type: Input
Alternate function: I/O Expander interrupt 2 input.
GPIO[5] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[6] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[7] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: GPEN
Alternate function pin type: Output
Alternate function: General Purpose Event (GPE) output.
GPIO[11] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P6RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 6.
Table 4 General Purpose I/O Pins
Signal Type Name/Description
Table 3 SMBus Interface Pins (Part 2 of 2)
6 of 30 May 10, 2016
IDT 89HPES10T4G2 Data Sheet
Signal Type Name/Description
CCLKDS I Common Clock Downstream. The assertion of this pin indicates that all
downstream ports are using the same clock source as that provided to
downstream devices.This bit is used as the initial value of the Slot Clock
Configuration bit in all of the Link Status Registers for downstream ports.
The value may be overridden by modifying the SCLK bit in each down-
stream port’s PCIELSTS register.
CCLKUS I Common Clock Upstream. The assertion of this pin indicates that the
upstream port is using the same clock source as the upstream device. This
bit is used as the initial value of the Slot Clock Configuration bit in the Link
Status Register for the upstream port. The value may be overridden by
modifying the SCLK bit in the P0_PCIELSTS register.
MSMBSMODE I Master SMBus Slow Mode. The assertion of this pin indicates that the
master SMBus should operate at 100 KHz instead of 400 KHz. This value
may not be overridden.
PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside
PES10T4G2 and initiates a PCI Express fundamental reset.
RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, PES10T4G2 executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device opera-
tion begins. The device exits the reset state when the RSTHALT bit is
cleared in the SWCTL register by an SMBus master.
SWMODE[2:0] I Switch Mode. These configuration pins determine the PES10T4G2 switch
operating mode.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 - through 0x7 Reserved
These pins should be static and not change following the negation of
PERSTN.
Table 5 System Pins
Signal Type Name/Description
JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
Table 6 Test Pins (Part 1 of 2)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

89HPES10T4G2ZBBCG8

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Description:
PCI Interface IC PCI EXPRESS SWITCH
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