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SSTUB32872AHLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
10
1222F—3/13/07
ICSSSTUB32872A
Advance Information
Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 2.5V
Input Voltage
1,
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
-0.5V to VDD +2.5V
Output Voltage
1,2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
-0.5V to VDDQ + 0.5V
Input Clamp Current . . . . . . . . . . . . . . . . . . . . ±50 mA
Output Clamp Current . . . . . . . . . . . . . . . . . . . ±50mA
Continuous Output Current. . . . . . . . . . . . . . . ±50mA
VDD or GND Current/Pin . . . . . . . . . . . . . . . . ±100mA
Package Thermal Impedance
3
. . . . . . . . . . . . . . .
36°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Notes:
1. The input and output negative voltage
ratings may be excluded if the input
and output clamp ratings are observed.
2. This value is limited to 2.5V maximum.
3. The package thermal impedance is
calculated in accordance with
JESD 51.
Recommended Operating Conditions
PARAMETER MIN TYP MAX UNITS
V
DDQ
1.7 1.8 1.9
V
REF
0.49 x V
DD
0.5 x V
DD
0.51 x V
DD
V
TT
V
REF
- 0.04 V
REF
V
REF
+ 0.04
V
I
Input Voltage 0 V
DDQ
V
IH
(
DC
)
DC Input High Voltage V
REF
+ 0.125
V
IH
(
AC
)
AC Input High Voltage V
REF
+ 0.250
V
IL
(
DC
)
DC Input Low Voltage V
REF
- 0.125
V
IL
(
AC
)
AC Input Low Voltage V
REF
- 0.250
V
IH
Input High Voltage Level 0.65 x V
DDQ
V
IL
Input Low Voltage Level 0.35 x V
DDQ
V
ICR
Common mode Input Range 0.675 1.125
V
ID
Differential Input Voltage 0.600
I
OH
-8
I
OL
8
T
A
070°C
1
Guaranteed by design, not 100% tested in production.
mA
Note: Rst and Cn inputs must be helf at valid logic levels (not floating) to ensure proper device operation. The
differential inputs must not be floating unless Rst is low.
V
DESCRIPTION
I/O Supply Voltage
Reference Voltage
Operating Free-Air Temperature
RESET
CK, CK
Low-Level Output Current
Termination Voltage
High-Level Output Current
Data Inputs
11
1222F—3/13/07
ICSSSTUB32872A
Advance Information
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range (See figure 7)
MIN MAX
dV/dt_r 1 4 V/ns
dV/dt_f 1 4 V/ns
dV/dt_Δ
1
1V/ns
1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
PARAMETER
V
DD
= 1.8V ± 0.1V
UNIT
Electrical Characteristics - DC
T
A
= 0 - 70°C; V
DD
= 2.5 +/-0.2V, V
DDQ
=2.5 +/-0.2V; (unless otherwise stated)
SYMBOL PARAMETERS V
DDQ
MIN TYP MAX UNITS
V
OH
I
OH
= -8mA 1.7V 1.2
V
OL
I
OL
= 8mA 1.7V 0.5
I
I
All Inputs V
I
= V
D
D
or GND 1.9V ±5 µA
Standby (Static) RESET = GND 200 µA
Operating (Static)
V
I
= V
IH(AC)
or V
IL(AC)
,
RESET = V
D
D
150
mA
Dynamic operating
(clock only)
RESET = V
DD
,
V
I
= V
IH(AC)
or V
IL(AC)
,
CLK and CLK switching
50% duty cycle.
TBD
µA/clock
MHz
Dynamic Operating
(per each data
input)
RESET = V
DD
,
V
I
= V
IH(AC)
or V
IL (AC)
,
CLK and CLK switching
50% duty cycle. One data
input switching at half
clock frequency, 50%
duty cycle
TBD
µA/ clock
MHz/data
Data Inputs 2.5 5
CLK and CLK 2 3.8
RESET 4.5 pF
Notes:
1 - Guaranteed by design, not 100% tested in production.
C
i
V
I
= V
DDQ
or GND
I
DD
I
DDD
I
O
= 0
CONDITIONS
V
I
= V
REF
±350mV
V
IC
R
= 1.25V, V
I
(
PP
)
= 360mV
pF
V
1.8V
1.9V
12
1222F—3/13/07
ICSSSTUB32872A
Advance Information
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
MIN MAX
f
clock
Clock frequency 410 MHz
t
W
Pulse duration 1 ns
t
ACT
Differential inputs active time 10 ns
t
INACT
Differential inputs inactive time 15 ns
t
S
Data before CK↑,
CK
↓ 0.6
DCS0
,
DSC1
before CK
↑
,
C
K
↓,
S
high
0.7
Hold time
DCS
, DODT, DCKE and Dn
after CK↑,
C
K
↓
0.6 ns
Hold time PAR_IN after CK
↑
,
CK
↓
0.5 ns
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
4 - CK/
C
K
signal input slew rate of 1V/ns.
SYMBOL
Notes:
t
H
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
V
DD
= 1.8V ±0.1V
UNITSPARAMETERS
nsSetup time
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
Symbol Parameter Measurement Conditions MIN MAX Units
fmax Max input clock frequency 410 MHz
t
PDM
Propagation delay, single
bit switchin
g
CK↑ and
CK
↓ to Qn 1.25 1.9 ns
t
LH
Low to High propagation
delay
1.2 3 ns
t
HL
High to low propagation
delay
0.9 3 ns
t
PDMSS
Propagation delay
simultaneous switchin
g
CK
↑
and
CK
↓
to Qn 2 ns
t
PHL
High to low propagation
delay
RESET
↓
to Qn
↓
3ns
t
PLH
Low to High propagation
delay
RESE
T↓ to
PTYERR
↑ 3ns
1. Guaranteed by desi
g
n, not 100% tested in production.
CK
↑
and
CK
↓
to
PTYERR
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

SSTUB32872AHLF

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Buffers & Line Drivers 1.8V LOW POWER WIDE RANGE
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