OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

SSTUB32872AHLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
16
1222F—3/13/07
ICSSSTUB32872A
Advance Information
3 Test circuits and switching waveforms (cont’d)
3.4 Partial-parity-out load circuit and voltage measurement information (V
DD
=1.8V±0.1V)
All input pulses are supplied by generators having the following characteristics: PRR 10 MHz;
Z
o
= 50 ; input slew rate = 1 V/ns ± 20%, unless otherwise specified.
(1) C
L
includes probe and jig capacitance.
Figure 32 — Partial-parity-out load circuit,
V
TT
= V
DD
/2
t
PLH
and t
PHL
are the same as t
PD
.
V
I(PP)
= 600 mV
Figure 33 — Partial-parity-out voltage waveforms; propagation delay times with respect to clock inputs
V
TT
= V
DD
/2
t
PLH
and t
PHL
are the same as t
PD
.
V
IH
= V
REF
+ 250 mV (AC voltage levels) for differential inputs. V
IH
= V
DD
for LVCMOS inputs.
V
IL
= V
REF
- 250 mV (AC voltage levels) for differential inputs. V
IL
= V
DD
for LVCMOS inputs.
Figure 34 — Partial-parity-out voltage waveforms; propagation delay times with respect to reset input
V
OH
V
OL
OUTPUT
t
PLH
002aaa375
V
TT
V
ICR
V
ICR
t
PHL
CK
CK
V
i(p-p)
t
PHL
002aaa376
LVCMOS RST
INPUT
OUTPUT
V
TT
V
DD
/2
V
IH
V
IL
V
OH
V
OL
DUT
Out
Test Point
R
L
=
C
L
=
5 pF
(see Note A)
1 k
Ω
Ω
17
1222F—3/13/07
ICSSSTUB32872A
Advance Information
Ordering Information
ICSSSTUB32872Az(LF)T
- e -
TYP
b
REF
b
REF
Alpha Designations
for Vertical Grid
(Letters I, O, Q & S
not used)
Alpha Designations
for Vertical Grid
(Letters I, O, Q & S
not used)
Numeric Designations
for Horizontal Grid
Numeric Designations
for Horizontal Grid
h
TYP
h
TYP
c
REF
c
REF
A
B
C
D
TOP VIEW
A1
3 2 1
4
Seating
Plane
Seating
Plane
C
T
0.12 C
d TYP
E
D
D1D1D1D1D1
- e -- e -
- e -
E1
TYP
TYP
Example:
Designation for tape and reel packaging
Lead Free, RoHS Compliant (Optional)
Package Type
H = LFBGA (reduced size: 5.5 x 13.50)
HM = TFBGA (reduced size: 5.0 x 11.50)
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
ICS XXXX y z (LF) T
D E T e HORIZ VERT TOTAL d h b c
Min/Max Min/Max Min/Max
13.50 Bsc 5.50 Bsc 1.20/1.40 0.80 Bsc 6 16 96 0.40/0.50 0.25/0.41 0.75 0.75
11.50 Bsc 5.00 Bsc 1.00/1.20 0.65 Bsc 6 16 96 0.35/0.45 0.25/0.35 0.875 0.875
MO-205
10-0055C
* Source Ref.: JEDEC Publication 95,
ALL DIMENSIONS IN MILLIMETERS
REF. DIMENSIONS ----- BALL GRID ----- Max.
Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used.
18
1222F—3/13/07
ICSSSTUB32872A
Advance Information
Revision History
Rev. Issue Date
Description
Page #
A 5/2/2006
Initial Release. -
B 12/12/2006
Electrical table, Ci Data input max changed from 3.5 to 5.0, CLK max
chan
g
ed from 3 to 3.8
11
C 12/20/2006
Timing table, ts Data before CK changed from 0.5 to 0.7, th DCS after CK
chan
g
ed from 0.5 to 0.6
12
D 12/21/2006
Applications, removed "800"; Electrical table, Idd Operating max changed
from 80 to 150, Ci RESET typ changed from 2.5 to 4.5; Timing table, th Hold
Time, changed Q to Dn, Switching table, changed tpdm max from 1.7 to 1.9,
thl min from 1 to 0.9, and tpdmss max from 1.9 to 2.
1, 11, 12
E 3/6/2007
Timing table, ts Data before CK changed from 0.7 to 0.6; Switching table,
fixed t
yp
os.
12
F 3/13/2007
Page 1, Recc. List, changed 3rd bullet to "Provides complete DDR DIMM
solution with ICS98ULPA877A, ICS97ULP877, or IDTCSPUA877A"; page 11,
fixed t
yp
os.
1, 11
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

SSTUB32872AHLF

Mfr. #:
Buy SSTUB32872AHLF
Manufacturer:
Description:
Buffers & Line Drivers 1.8V LOW POWER WIDE RANGE
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet