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SSTUB32872AHLF
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
7
1222F—3/13/07
ICSSSTUB32872A
Advance Information
Register Timing
CK
Dn
(1)
Qn
t
su
CK
n
n
+ 1
n + 2
n
+ 3
n + 4
DCSn
RESET
t
ACT
t
h
t
PDM
, t
PDMSS
CK to Q
P
ARIN
t
su
t
h
t
PHL
, t
PLH
CK to PTYERR
t
PHL
CK to PTYERR
PTYERR
H, L, or X
H or L
(1) After RE
SE
T is s
witched
fro
m LOW
to HI
GH, all d
ata and
PARIN inpu
t signals mus
t be s
et and
held L
OW
for
a
minimum t
ime of
t (max) to a
void
fals
e err
or.
ACT
Figure
4 R
ES
ET
switc
hes from
L t
o H
—
8
1222F—3/13/07
ICSSSTUB32872A
Advance Information
Register Timing
Fi
gure
5
— RESET b
ein
g hel
d HIGH
CK
Dn
(1)
Qn
t
su
002aaa984
CK
n
n + 1
n + 2
n + 3
n + 4
DCSn
RESET
t
h
t
PDM
, t
PDMSS
CK to Q
P
ARIN
t
h
t
PHL
, t
PLH
CK to PTYERR
PTYERR
Output signal is dependent on the pr
ior unkno
wn e
vent
H or L
Unkno
wn input e
v
ent
t
su
9
1222F—3/13/07
ICSSSTUB32872A
Advance Information
Register Timing
Figur
e
6
—
RE
SET
CK
(1)
DCSn
RESET
t
INA
CT
t
RPHL
RESET to Q
PA R I
N
(1)
t
RPLH
RESET to PTYERR
PTYERR
H, L, or X
H or L
CK
(1)
Dn
(1)
Qn
switches from H to L
(1) After Reset is switched from HIGH to LOW, all data and clock input signals must be set and held at valid logic
levels (not floating) for a minimum time of t (max)
INACT
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
SSTUB32872AHLF
Mfr. #:
Buy SSTUB32872AHLF
Manufacturer:
Description:
Buffers & Line Drivers 1.8V LOW POWER WIDE RANGE
Lifecycle:
New from this manufacturer.
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