IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
14
Figure 2. Dynamic Bus Sizing (Continued)
(1) Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with unused
inputs) must not be left open, rather they must be either HIGH or LOW.
Figure 3. Logic Diagrams for SIZ0, SIZ1, and
BEBE
BEBE
BE
Register
D
C
(d) BYTE SIZE ⎯ LITTLE-ENDIAN
1st: Read from FIFO1/
Write to FIFO2
2nd: Read from FIFO1/
Write to FIFO2
A
B
3rd: Read from FIFO1/
Write to FIFO2
4th: Read from FIFO1/
Write to FIFO2
BE SIZ1 SIZ0
H H L
4663 drw fi
01a
B35⎯B27 B26⎯B18 B17⎯B9 B8⎯B0
B35⎯B27 B26⎯B18 B17⎯B9 B8⎯B0
B35⎯B27 B26⎯B18 B17⎯B9 B8⎯B0
B35⎯B27 B26⎯B18 B17⎯B9 B8⎯B0
MUX
G1
1
1
D Q
SIZ0 Q
SIZ1 Q
BE
Q
SIZ0
SIZ1
BE
CLKB
4663 drw fig 02
