IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
25
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and
rising CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown.
2. Port B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the last
word or byte of the long word, respectively.
Figure 16.
FFAFFA
FFAFFA
FFA
Flag Timing and First Available Write when FIFO1 is Full.
CSB
EFB
SIZ1,
SIZ0
ENB
B0 - B35
CLKB
FFA
CLKA
CSA
4663 drw 16
WRA
12
A0 - A35
MBA
ENA
t
CLK
t
CLKH
t
CLKL
t
ENS
t
ENH
t
A
t
SKEW1
t
CLK
t
CLKH
t
CLKL
t
ENS
t
ENS
t
DS
t
ENH
t
ENH
t
DH
To FIFO1
Previous Word in FIFO1 Output Register
Next Word From FIFO1
LOW
W/RB
LOW
LOW
HIGH
LOW
HIGH
(1)
FIFO1 Full
t
WFF
t
WFF
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
26
Figure 17.
FFBFFB
FFBFFB
FFB
Flag Timing and First Available Write when FIFO2 is Full
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, either SIZ1 = LOW or SIZ0 = LOW).
3. Port B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, AEB is set LOW by the last word or byte read of the long word,
respectively.
Figure 18. Timing for
AEBAEB
AEBAEB
AEB
when FIFO1 is Almost-Empty
CSA
EFA
MBA
ENA
A0 - A35
CLKA
FFB
CLKB
CSB
4663 drw 17
WRB
12
B0 - B35
SIZ1,
SIZ0
ENB
t
CLK
t
CLKH
t
CLKL
t
ENS
t
ENH
t
A
t
SKEW1
t
CLK
t
CLKH
t
CLKL
t
ENS
t
ENS
t
DS
t
ENH
t
ENH
t
DH
To FIFO2
Previous Word in FIFO2 Output Register
Next Word From FIFO2
LOW
W/RA
LOW
LOW
HIGH
LOW
HIGH
(1)
FIFO2 Full
t
WFF
t
WFF
AEB
CLKA
ENB
4663 drw 18
ENA
CLKB
2
1
t
ENS
t
ENH
t
SKEW2
t
PAE
t
PAE
t
ENS
t
ENH
X Long Word in FIFO1
(X+1) Long Words in FIFO1
(1)
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than tSKEW1, then FFB may transition HIGH one CLKB cycle later than shown.
2. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, FFB is set LOW by the last word or byte write of the long word,
respectively.
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
27
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and
rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (CSB = LOW, W/RB = HIGH, either SIZ0 = LOW or SIZ1 = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW).
3. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW2 is referenced from the rising CLKB edge that writes the last
word or byte of the long word, respectively.
Figure 19. Timing for
AEAAEA
AEAAEA
AEA
when FIFO2 is Almost-Empty
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, either SIZ0 = LOW or SIZ1 = LOW).
3. Port B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW2 is referenced from the last word or byte read of the long word,
respectively.
Figure 20. Timing for
AFAAFA
AFAAFA
AFA
when FIFO1 is Almost-Full
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and
rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKB cycle later than shown.
2. FIFO2 Write (CSB = LOW, W/RB = HIGH, either SIZ0 = LOW or SIZ1 = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW).
3. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, AFB is set LOW by the last word or byte read of the long word,
respectively.
Figure 21. Timing for
AFBAFB
AFBAFB
AFB
when FIFO2 is Almost-Full
AEA
CLKB
ENA
4663 drw 19
ENB
CLKA
2
1
t
ENS
t
ENH
t
SKEW2
t
PAE
t
PAE
t
ENS
t
ENH
(X+1) Long Words in FIFO2
X Long Words in FIFO2
(1)
AFA
CLKA
ENB
4663 drw 20
ENA
CLKB
12
tSKEW2
tENS
tENH
tPAF
tENS tENH
tPAF
[64-(X+1)] Long Words in FIFO1
(64-X) Long Words in FIFO1
(1)
AFB
CLKB
ENA
4663 drw 21
ENB
CLKA
12
t
SKEW2
t
ENS
t
ENH
t
ENS
t
ENH
t
PAF
[64-(X+1)] Long Words in FIFO2
(64-X) Long Words in FIFO2
(1)
t
PAF

72V3614L15PF

Mfr. #:
Manufacturer:
IDT
Description:
FIFO 64 x 36 x 2 SyncBiFIFO, 3.3V
Lifecycle:
New from this manufacturer.
Delivery:
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