BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2COMMERCIAL TEMPERATURE RANGE
22
NOTES:
1.SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35.
2.Unused bytes B9-B35 or B0-B26 are indeterminate.
Figure 12. Port-B Byte Read Cycle Timing for FIFO1
DATA WRITTEN TO FIFO 1SWAP MODEREADBIG-LITTLE-
NO.ENDIANENDIAN
A35-A27A26-A18A17-A9A8-A0SW1SW0B35-B27B8-B0
1AD
2BC
ABCDLL3CB
4DA
1DA
2CB
ABCDLH3BC
4AD
1CB
2DA
ABCDHL3AD
4BC
1BC
2AD
ABCDHH3DA
4CB
DATA READ FROM FIFO 1
DATA SWAP TABLE FOR BYTE READS FROM FIFO1
EFB
CSB
W/RB
SIZ1,
SIZ0
ENB
CLKB
4663 drw 12
HIGH
SW1,
SW0
BE
PGB,
ODD/
EVEN
B0-B8
B27-B35
Read 4Read 1Read 2
Read 4Read 1Read 3
Read 3Previous Data
Previous Data
Read 2
(1,0)(1,0)(1,0)
Not (1,1)
(1)
No Operation
t
DIS
t
DIS
t
A
t
A
t
A
t
A
t
A
t
A
t
EN
t
PGH
t
PGS
Not (1,1)
(1)
Not (1,1)
(1)
Not (1,1)
(1)
(1,0)
t
ENS
t
ENH
t
SWS
t
SWH
t
SZH
t
SZH
t
SZS
t
SZS
t
A
t
A
Little-
Endian
Big-
Endian
(2)
(2)
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2COMMERCIAL TEMPERATURE RANGE
23
NOTE:
1.Read from FIFO2.
Figure 13. Port-A Read Cycle Timing for FIFO2
NOTES:
1.tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and
rising CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
2.Port-B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port-B size is word or byte, EFB is set LOW by the last word or byte read from FIFO1, respec-
tively.
Figure14.
EFBEFB
EFBEFB
EFB
Flag Timing and First Data Read when FIFO1 is Empty
4663 drw 13
CLKA
EFA
ENA
A0 - A35
MBA
CSA
W/RA
t
CLK
t
CLKH
t
CLKL
t
ENS
t
A
t
MDV
t
EN
t
A
t
ENS
t
ENH
t
ENS
t
ENH
Previous Data
Word 1Word 2
(1)(1)
t
ENH
t
DIS
No Operation
PGA,
ODD/
EVEN
HIGH
t
PGH
t
PGS
t
PGH
t
PGS
CSA
WRA
MBA
FFA
A0 - A35
CLKB
EFB
CSB
W/RB
SIZ1,
SIZ0
ENA
ENB
B0 -B35
CLKA
12
4663 drw 14
t
CLKH
t
CLKL
t
CLK
t
ENS
t
ENS
t
ENH
t
ENH
t
DS
t
DH
t
SKEW1
t
CLK
t
CLKL
t
ENS
t
ENH
t
A
W1
FIFO1 Empty
LOW
HIGH
LOW
LOW
LOW
t
CLKH
W1
HIGH
(1)
t
REF
t
REF
IDT72V3614 3.3V, CMOS SyncBiFIFO
TM
WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2COMMERCIAL TEMPERATURE RANGE
24
NOTES:
1.tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and
rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
2.Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte tSKEW1 is referenced to the rising CLKB edge that writes the last word or
byte of the long word, respectively.
Figure 15.
EFAEFA
EFAEFA
EFA
Flag Timing and First Data Read when FIFO2 is Empty
