ISL1208IRT8Z-TK Datasheet ISL1208IB8Z-TK, ISL1208IU8Z-TK, ISL1208IU8Z | P13-P15

FN8085.8

September 12, 2008

FREQUENCY OUT CONTROL BITS (FO <3:0>)

These bits enable/disable the frequency output function and

select the output frequency at the IRQ/fOUT pin. See

Table 4 for frequency selection. When the frequency mode is

enabled, it will override the alarm mode at the IRQ

/fOUT pin.

FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB)

This bit enables/disables the fOUT/IRQ

pin during battery

backup mode (i.e. V

BAT

power source active). When the

FOBATB is set to “1” the fOUT/IRQ

pin is disabled during

battery backup mode. This means that both the frequency

output and alarm output functions are disabled. When the

FOBATB is cleared to “0”, the fOUT/IRQ

pin is enabled

during battery backup mode.

LOW POWER MODE BIT (LPMODE)

This bit enables/disables low power mode. With

LPMODE = “0”, the device will be in normal mode and the

BAT

supply will be used when V

< V

BAT

- V

BATHYS

and

< V

TRIP

. With LPMODE = “1”, the device will be in low

power mode and the V

BAT

supply will be used when

< V

BAT

-V

BATHYS

. There is a supply current saving of

about 600nA when using LPMODE = “1” with V

= 5V.

(See Typical Performance Curves on page 7: I

vs V

with LPMODE ON and OFF.) Avoid setting the device into

low power mode with V

< V

BAT

, the I2C communications

will stop permanently. The V

BAT

input must be lowered

below V

to resume communications.

ALARM ENABLE BIT (ALME)

This bit enables/disables the alarm function. When the ALME

bit is set to “1”, the alarm function is enabled. When the ALME

is cleared to “0”, the alarm function is disabled. The alarm

function can operate in either a single event alarm or a periodic

interrupt alarm (see IM bit).

NOTE: When the frequency output mode is enabled, the alarm function

is disabled.

INTERRUPT/ALARM MODE BIT (IM)

This bit enables/disables the interrupt mode of the alarm

function. When the IM bit is set to “1”, the alarm will operate

in the interrupt mode, where an active low pulse width of

250ms will appear at the IRQ

/fOUT pin when the RTC is

triggered by the alarm as defined by the alarm registers (0Ch

to 11h). When the IM bit is cleared to “0”, the alarm will

operate in standard mode, where the IRQ

/fOUT pin will be

tied low until the ALM status bit is cleared to “0”.

Analog Trimming Register

ANALOG TRIMMING REGISTER (ATR<5:0>)

Six analog trimming bits, ATR0 to ATR5, are provided in

order to adjust the on-chip load capacitance value for

frequency compensation of the RTC. Each bit has a different

weight for capacitance adjustment. For example, using a

Citizen CFS-206 crystal with different ATR bit combinations

provides an estimated ppm adjustment range from -34ppm

to +80ppm to the nominal frequency compensation. The

combination of analog and digital trimming can give up to

-94ppm to +140ppm of total adjustment.

The effective on-chip series load capacitance, C

LOAD

ranges from 4.5pF to 20.25pF with a mid-scale value of

12.5pF (default). C

LOAD

is changed via two digitally

controlled capacitors, C

and C

, connected from the X1

and X2 pins to ground (see Figure 11). The value of C

and

are given in Equation 1:

TABLE 4. FREQUENCY SELECTION OF fOUT PIN

FREQUENCY,

OUT

UNITS FO3 FO2 FO1 FO0

0 Hz0 000

32768 Hz 0 0 0 1

4096 Hz 0 0 1 0

1024 Hz 0 0 1 1

64 Hz0 100

32 Hz0 101

16 Hz0 110

8 Hz0 111

4 Hz1 000

2 Hz1 001

1 Hz1 010

1/2 Hz1 011

1/4 Hz1 100

1/8 Hz1 101

1/16 Hz 1 1 1 0

1/32 Hz 1 1 1 1

IM BIT INTERRUPT/ALARM FREQUENCY

0 Single Time Event Set By Alarm

1 Repetitive/Recurring Time Event Set By Alarm

FIGURE 11. DIAGRAM OF ATR

CRYSTAL

OSCILLATOR

16 b5⋅ 8b4 4b3 2b2 1b1 0.5b0 9+⋅+⋅+⋅+⋅+⋅+()pF=

(EQ. 1)

ISL1208

FN8085.8

September 12, 2008

The effective series load capacitance is the combination of

and C

in Equation 2.:

For example, C

LOAD

(ATR = 00000) = 12.5pF, C

LOAD

(ATR =

100000) = 4.5pF, and C

LOAD

(ATR = 011111) = 20.25pF. The

entire range for the series combination of load capacitance

goes from 4.5pF to 20.25pF in 0.25pF steps. Note that these

are typical values.

BATTERY MODE ATR SELECTION (BMATR <1:0>)

Since the accuracy of the crystal oscillator is dependent on

the V

BAT

operation, the ISL1208 provides the capability

to adjust the capacitance between V

and V

BAT

when the

device switches between power sources.

DIGITAL TRIMMING REGISTER (DTR <2:0>)

The digital trimming bits DTR0, DTR1, and DTR2 adjust the

average number of counts per second and average the ppm

error to achieve better accuracy.

• DTR2 is a sign bit. DTR2 = “0” means frequency

compensation is >0. DTR2 = “1” means frequency

compensation is <0.

• DTR1 and DTR0 are both scale bits. DTR1 gives 40ppm

adjustment and DTR0 gives 20ppm adjustment.

A range from -60ppm to +60ppm can be represented by

using these three bits (see Table 5).

Alarm Registers

Addresses [0Ch to 11h]

The alarm register bytes are set up identical to the RTC

an enable bit (enable = “1”). These enable bits specify which

alarm registers (seconds, minutes, etc.) are used to make

the comparison. Note that there is no alarm byte for year.

The alarm function works as a comparison between the

alarm registers and the RTC registers. As the RTC

advances, the alarm will be triggered once a match occurs

between the alarm registers and the RTC registers. Any one

alarm register, multiple registers, or all registers can be

enabled for a match.

There are two alarm operation modes: Single Event and

periodic Interrupt Mode:

• Single Event Mode is enabled by setting the ALME bit to

“1”, the IM bit to “0”, and disabling the frequency output.

This mode permits a one-time

match between the alarm

registers and the RTC registers. Once this match occurs,

the ALM bit is set to “1” and the IRQ

output will be pulled

low and will remain low until the ALM bit is reset. This can

be done manually or by using the auto-reset feature.

• Interrupt Mode is enabled by setting the ALME bit to “1”,

the IM bit to “1”, and disabling the frequency output. The

IRQ

output will now be pulsed each time an alarm occurs.

This means that once the interrupt mode alarm is set, it

will continue to alarm for each occurring match of the

alarm and present time. This mode is convenient for

hourly or daily hardware interrupts in microcontroller

applications such as security cameras or utility meter

reading.

To clear an alarm, the ALM bit in the status register must be

set to “0” with a write. Note that if the ARST bit is set to 1

(address 07h, bit 7), the ALM bit will automatically be cleared

when the status register is read.

BMATR1 BMATR0

DELTA

CAPACITANCE

BAT

TO C

VDD

)

0 0 0pF

0 1 -0.5pF (≈ +2ppm)

1 0 +0.5pF (≈ -2ppm)

1 1 +1pF (≈ -4ppm)

LOAD

-----------

⎝⎠

⎛⎞

-----------------------------------

LOAD

16 b5

⋅ 8 b4 4 b3 2 b2 1 b1 0.5 b0 9+⋅+⋅+⋅+⋅+⋅+

-----------------------------------------------------------------------------------------------------------------------------

⎝⎠

⎛⎞

(EQ. 2)

TABLE 5. DIGITAL TRIMMING REGISTERS

DTR REGISTER ESTIMATED

FREQUENCY

PPMDTR2 DTR1 DTR0

0 0 0 0 (default)

001 +20

010 +40

011 +60

100 0

101 -20

110 -40

111 -60

ISL1208

FN8085.8

September 12, 2008

Below are examples of both Single Event and periodic

Interrupt Mode alarms.

Example 1 – Alarm set with single interrupt (IM=”0”)

A single alarm will occur on January 1 at 11:30am.

A. Set Alarm registers as follows:

B. Also the ALME bit must be set as follows:

xx indicate other control bits

After these registers are set, an alarm will be generated when

the RTC advances to exactly 11:30am on January 1 (after

seconds changes from 59 to 00) by setting the ALM bit in the

status register to “1” and also bringing the IRQ

output low.

Example 2 – Pulsed interrupt once per minute (IM=”1”)

Interrupts at one minute intervals when the seconds register

is at 30 seconds.

A. Set Alarm registers as follows:

B. Set the Interrupt register as follows:

xx indicate other control bits

Once the registers are set, the following waveform will be

seen at IRQ-:

Note that the status register ALM bit will be set each time the

alarm is triggered, but does not need to be read or cleared.

User Registers

Addresses [12h to 13h]

These registers are 2 bytes of battery-backed user memory

storage.

C Serial Interface

The ISL1208 supports a bidirectional bus oriented protocol.

The protocol defines any device that sends data onto the

bus as a transmitter and the receiving device as the receiver.

The device controlling the transfer is the master and the

device being controlled is the slave. The master always

initiates data transfers and provides the clock for both

transmit and receive operations. Therefore, the ISL1208

operates as a slave device in all applications.

All communication over the I

C interface is conducted by

sending the MSB of each byte of data first.

Protocol Conventions

Data states on the SDA line can change only during SCL

LOW periods. SDA state changes during SCL HIGH are

reserved for indicating START and STOP conditions (See

Figure 12). On power-up of the ISL1208, the SDA pin is in

the input mode.

All I

C interface operations must begin with a START

condition, which is a HIGH to LOW transition of SDA while

SCL is HIGH. The ISL1208 continuously monitors the SDA

and SCL lines for the START condition and does not

respond to any command until this condition is met (See

Figure 12). A START condition is ignored during the

power-up sequence.

All I

C interface operations must be terminated by a STOP

condition, which is a LOW to HIGH transition of SDA while

SCL is HIGH (See Figure 12). A STOP condition at the end

of a read operation or at the end of a write operation to

memory only places the device in its standby mode.

An acknowledge (ACK) is a software convention used to

indicate a successful data transfer. The transmitting device,

either master or slave, releases the SDA bus after

transmitting eight bits. During the ninth clock cycle, the

ALARM

BIT

DESCRIPTION76543210HEX

SCA 00000000 00hSeconds disabled

MNA 10110000B0hMinutes set to 30,

enabled

HRA 10010001 91hHours set to 11,

enabled

DTA 10000001 81hDate set to 1,

enabled

MOA 10000001 81hMonth set to 1,

enabled

DWA 00000000 00hDay of week

disabled

CONTROL

BIT

DESCRIPTION76543210HEX

INT 01xx0000 x0hEnable Alarm

ALARM

BIT

DESCRIPTION76543210HEX

SCA 10110000B0hSeconds set to 30,

enabled

MNA 0000000000hMinutes disabled

HRA 0000000000hHours disabled

DTA 0000000000hDate disabled

MOA 0000000000hMonth disabled

DWA 0000000000hDay of week disabled

CONTROL

BIT

DESCRIPTION76543210HEX

INT 11xx0000x0hEnable Alarm and Int

Mode

60s

RTC AND ALARM REGISTERS ARE BOTH “30”s

ISL1208

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

ISL1208IRT8Z-TK

Mfr. #:

Buy ISL1208IRT8Z-TK

Manufacturer:

Renesas / Intersil

Description:

Real Time Clock I2CAL TIME CLK/CLNDR 8LD 3X3

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

ISL1208IRT8Z-TK

ISL1208IRT8Z-TK

Products related to this Datasheet