16
FN8085.8
September 12, 2008
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 13).
The ISL1208 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL1208 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
FIGURE 12. VALID DATA CHANGES, START, AND STOP CONDITIONS
FIGURE 13. ACKNOWLEDGE RESPONSE FROM RECEIVER
FIGURE 14. BYTE WRITE SEQUENCE
SDA
SCL
START
DATA DATA
STOP
STABLE CHANGE
DATA
STABLE
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
81 9
START ACK
SCL FROM
MASTER
HIGH IMPEDANCE
HIGH IMPEDANCE
S
T
A
R
T
S
T
O
P
IDENTIFICATION
BYTE
DATA
BYTE
A
C
K
SIGNALS FROM
THE MASTER
SIGNALS FROM
THE ISL1208
A
C
K
10011
A
C
K
WRITE
SIGNAL AT SDA
0000111
ADDRESS
BYTE
ISL1208
17
FN8085.8
September 12, 2008
Device Addressing
Following a start condition, the master must output a Slave
Address Byte. The 7 MSBs are the device identifier. These
bits are “1101111”. Slave bits “1101” access the register.
Slave bits “111” specify the device select bits.
The last bit of the Slave Address Byte defines a read or write
operation to be performed. When this R/W
bit is a “1”, then a
read operation is selected. A “0” selects a write operation
(Refer to Figure 15).
After loading the entire Slave Address Byte from the SDA
bus, the ISL1208 compares the device identifier and device
select bits with “1101111”. Upon a correct compare, the
device outputs an acknowledge on the SDA line.
Following the Slave Byte is a one byte word address. The
word address is either supplied by the master device or
obtained from an internal counter. On power-up the internal
address counter is set to address 0h, so a current address
read of the CCR array starts at address 0h. When required,
as part of a random read, the master must supply the 1 Word
Address Bytes as shown in Figure 16.
In a random read operation, the slave byte in the “dummy
write” portion must match the slave byte in the “read”
section. For a random read of the Clock/Control Registers,
the slave byte must be1101111x in both places.
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL1208 responds with an ACK. At this time, the I
2
C
interface enters a standby state.
Read Operation
A Read operation consists of a three byte instruction
followed by one or more Data Bytes (See Figure 16). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the R/W
bit
set to “0”, an Address Byte, a second START, and a second
Identification byte with the R/W
bit set to “1”. After each of
the three bytes, the ISL1208 responds with an ACK. Then
the ISL1208 transmits Data Bytes as long as the master
responds with an ACK during the SCL cycle following the
eighth bit of each byte. The master terminates the read
operation (issuing a STOP condition) following the last bit of
the last Data Byte (See Figure 16).
The Data Bytes are from the memory location indicated by
an internal pointer. This pointer initial value is determined by
the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 13h the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.
FIGURE 15. SLAVE ADDRESS, WORD ADDRESS, AND DATA
BYTES
SLAVE
ADDRESS BYTE
D7 D6 D5 D2D4 D3 D1 D0
A0A7 A2A4 A3 A1
DATA BYTE
A6 A5
1
10
1
1
1
R/W
1
WORD ADDRESS
FIGURE 16. READ SEQUENCE
SIGNALS
FROM THE
MASTER
SIGNALS FROM
THE SLAVE
SIGNAL AT
SDA
S
T
A
R
T
IDENTIFICATION
BYTE WITH
R/W
= 0
ADDRESS
BYTE
A
C
K
A
C
K
0
S
T
O
P
A
C
K
1
IDENTIFICATION
BYTE WITH
R/W
= 1
A
C
K
S
T
A
R
T
LAST READ
DATA BYTE
FIRST READ
DATA BYTE
A
C
K
101 1111
101
11
11
ISL1208
18
FN8085.8
September 12, 2008
Application Section
Oscillator Crystal Requirements
The ISL1208 uses a standard 32.768kHz crystal. Either
through hole or surface mount crystals can be used. Table 6
lists some recommended surface mount crystals and the
parameters of each. This list is not exhaustive and other
surface mount devices can be used with the ISL1208 if their
specifications are very similar to the devices listed. The
crystal should have a required parallel load capacitance of
12.5pF and an equivalent series resistance of less than 50k.
The crystal’s temperature range specification should match
the application. Many crystals are rated for -10°C to +60°C
(especially through hole and tuning fork types), so an
appropriate crystal should be selected if extended
temperature range is required.
Crystal Oscillator Frequency Adjustment
The ISL1208 device contains circuitry for adjusting the
frequency of the crystal oscillator. This circuitry can be used
to trim oscillator initial accuracy as well as adjust the
frequency to compensate for temperature changes.
The Analog Trimming Register (ATR) is used to adjust the
load capacitance seen by the crystal. There are six bits of
ATR control, with linear capacitance increments available for
adjustment. Since the ATR adjustment is essentially “pulling”
the frequency of the oscillator, the resulting frequency
changes will not be linear with incremental capacitance
changes. The equations which govern pulling show that
lower capacitor values of ATR adjustment will provide larger
increments. Also, the higher values of ATR adjustment will
produce smaller incremental frequency changes. These
values typically vary from 6ppm to 10 ppm/bit at the low end
to <1ppm/bit at the highest capacitance settings. The range
afforded by the ATR adjustment with a typical surface mount
crystal is typically -34ppm to +80ppm around the ATR=0
default setting because of this property. The user should
note this when using the ATR for calibration. The
temperature drift of the capacitance used in the ATR control
is extremely low, so this feature can be used for temperature
compensation with good accuracy.
In addition to the analog compensation afforded by the
adjustable load capacitance, a digital compensation feature
is available for the ISL1208. There are 3 bits known as the
Digital Trimming Register (DTR). The range provided is
±60ppm in increments of 20ppm. DTR operates by adding or
skipping pulses in the clock counter. It is very useful for
coarse adjustments of frequency drift over temperature or
extending the adjustment range available with the ATR
register.
Initial accuracy is best adjusted by enabling the frequency
output (using the INT register, address 08h), and monitoring
the ~IRQ/fOUT pin with a calibrated frequency counter. The
frequency used is unimportant, although 1Hz is the easiest
to monitor. The gating time should be set long enough to
ensure accuracy to at least 1ppm. The ATR should be set to
the center position, or 100000Bh, to begin with. Once the
initial measurement is made, then the ATR register can be
changed to adjust the frequency. Note that increasing the
ATR register for increased capacitance will lower the
frequency, and vice-versa. If the initial measurement shows
the frequency is far off, it will be necessary to use the DTR
register to do a coarse adjustment. Note that most all
crystals will have tight enough initial accuracy at room
temperature so that a small ATR register adjustment should
be all that is needed.
Temperature Compensation
The ATR and DTR controls can be combined to provide
crystal drift temperature compensation. The typical
32.768kHz crystal has a drift characteristic that is similar to
that shown in Figure 17. There is a turnover temperature
(T
0
) where the drift is very near zero. The shape is parabolic
as it varies with the square of the difference between the
actual temperature and the turnover temperature.
If full industrial temperature compensation is desired in an
ISL1208 circuit, then both the DTR and ATR registers will
need to be utilized (total correction range = -94ppm to
+140ppm).
TABLE 6. SUGGESTED SURFACE MOUNT CRYSTALS
MANUFACTURER PART NUMBER
Citizen CM200S
Epson MC-405, MC-406
Raltron RSM-200S
SaRonix 32S12
Ecliptek ECPSM29T-32.768K
ECS ECX-306
Fox FSM-327
TEMPERATURE (°C)
-160
-140
-120
-100
-80
-60
-40
-20
0
-40-30-20-100 1020304050607080
PPM
FIGURE 17. RTC CRYSTAL TEMPERATURE DRIFT
ISL1208

ISL1208IRT8Z-TK

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Real Time Clock I2CAL TIME CLK/CLNDR 8LD 3X3
Lifecycle:
New from this manufacturer.
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