PX1011A-EL1/G,557 Datasheet PX1011A-EL1,551, PX1011A-EL1/G,557, PX1011AI-EL1/G,551 | P1-P3

1. General description

The PX1011A/PX1012A is a high-performance, low-power, single-lane PCI Express

electrical PHYsical layer (PHY) that handles the low level PCI Express protocol and

signaling. The PX1011A/1012A PCI Express PHY is compliant to the

PCI Express Base

Speciﬁcation, Rev. 1.0a

, and

Rev. 1.1

. The PX1011A/1012A includes features such as

clock and data recovery (CDR), data serialization and de-serialization, 8b/10b encoding,

analog buffers, elastic buffer and receiver detection, and provides superior performance to

the Media Access Control (MAC) layer devices.

The PX1011A/1012A is a 2.5 Gbit/s PCI Express PHY with 8-bit data PXPIPE interface.

Its PXPIPE interface is a superset of the PHY Interface for the PCI Express (PIPE)

speciﬁcation, enhanced and adapted for off-chip applications with the introduction of a

source synchronous clock for transmit and receive data. The 8-bit data interface operates

at 250 MHz with SSTL_2 signaling. The SSTL_2 signaling is compatible with the I/O

interfaces available in FPGA products.

The PX1011A/1012A PCI Express PHY supports advanced power management

functions. The PX1011AI/PX1012AI is for the industrial temperature range (−40 °C to

+85 °C).

2. Features

2.1 PCI Express interface

n Compliant to

PCI Express Base Speciﬁcation 1.1

n Single PCI Express 2.5 Gbit/s lane

n Data and clock recovery from serial stream

n Serializer and De-serializer (SerDes)

n Receiver detection

n 8b/10b coding and decoding, elastic buffer and word alignment

n Supports loopback

n Supports direct disparity control for use in transmitting compliance pattern

n Supports lane polarity inversion

n Low jitter and Bit Error Rate (BER)

2.2 PHY/MAC interface

n Based on Intel PHY Interface for PCI Express architecture v1.0 (PIPE)

n Adapted for off-chip with additional synchronous clock signals (PXPIPE)

n 8-bit parallel data interface for transmit and receive at 250 MHz

n 2.5 V SSTL_2 class I signaling

PX1011A/PX1012A

PCI Express stand-alone X1 PHY

Rev. 02 — 18 May 2006 Product data sheet

Product data sheet Rev. 02 — 18 May 2006 2 of 32

Philips Semiconductors

PX1011A/PX1012A

PCI Express stand-alone X1 PHY

2.3 JTAG interface

n JTAG (IEEE 1149.1) boundary scan interface

n Built-In Self Test (BIST) controller tests SerDes and I/O blocks at speed

n 3.3 V CMOS signaling

2.4 Power management

n Dissipates < 300 mW in L0 normal mode

n Support power management of L0, L0s and L1

2.5 Clock

n 100 MHz external reference clock with ±300 ppm tolerance

n Supports spread spectrum clock to reduce EMI

n On-chip reference clock termination

2.6 Miscellaneous

n LFBGA81 lead or lead free package

n Operating ambient temperature

u Commercial: 0 °C to +70 °C

u Industrial: −40 °C to +85 °C

n ESD protection voltage for Human Body Model (HBM): 2000 V

3. Quick reference data

Table 1. Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

DDD1

digital supply voltage 1 for JTAG I/O 3.0 3.3 3.6 V

DDD2

digital supply voltage 2 for SSTL_2 I/O 2.3 2.5 2.7 V

DDD3

digital supply voltage 3 for core 1.2 1.25 1.3 V

supply voltage for high-speed

serial I/O and PVT

1.15 1.2 1.25 V

DDA1

analog supply voltage 1 for serializer 1.2 1.25 1.3 V

DDA2

analog supply voltage 2 for serializer 3.0 3.3 3.6 V

clk(ref)

reference clock frequency 99.97 100 100.03 MHz

amb

ambient temperature operating

commercial 0 - +70 °C

industrial −40 - +85 °C

Product data sheet Rev. 02 — 18 May 2006 3 of 32

Philips Semiconductors

PX1011A/PX1012A

PCI Express stand-alone X1 PHY

4. Ordering information

5. Marking

[1] Industrial temperature range.

Table 2. Ordering information

Type number Solder process Package

Name Description Version

PX1011A-EL1 SnPb solder ball

compound

LFBGA81 plastic low proﬁle ﬁne-pitch ball grid array package;