PX1011A_PX1012A_2 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 18 May 2006 6 of 32
Philips Semiconductors
PX1011A/PX1012A
PCI Express stand-alone X1 PHY
7.2 Pin description
The PHY input and output pins are described in Table 5 to Table 12. Note that input and
output is defined from the perspective of the PHY. Thus a signal on a pin described as an
output is driven by the PHY and a signal on a pin described as an input is received by the
PHY. A basic description of each pin is provided.
Table 5. PCI Express serial data lines
Symbol Pin Type Signaling Description
RX_P E1 input PCIe I/O differential input receive pair with 50 Ω
on-chip termination
RX_N F1 input PCIe I/O
TX_P H1 output PCIe I/O differential output transmit pair with
50 Ω on-chip termination
TX_N J1 output PCIe I/O
Table 6. PXPIPE interface transmit data signals
Symbol Pin Type Signaling Description
TXDATA[7:0] J9, H9, G8, G9,
F8, F9, E9, D9
input SSTL_2 8-bit transmit data input from the MAC
to the PHY
TXDATAK J7 input SSTL_2 selection input for the symbols of
transmit data; LOW = data byte;
HIGH = control byte
Table 7. PXPIPE interface receive data signals
Symbol Pin Type Signaling Description
RXDATA[7:0] B3, A3, B4, A4,
A5, B6, A6, B7
output SSTL_2 8-bit receive data output from the PHY
to the MAC
RXDATAK A7 output SSTL_2 selection output for the symbols of
receive data; LOW = data byte;
HIGH = control byte
Table 8. PXPIPE interface command signals
Symbol Pin Type Signaling Description
RXDET_ LOOPB H7 input SSTL_2 used to tell the PHY to begin a receiver
detection operation or to begin loopback;
LOW = reset state
TXIDLE H4 input SSTL_2 forces TX output to electrical idle. TXIDLE
should be asserted while in power states P0s
and P1.
TXCOMP J5 input SSTL_2 used when transmitting the compliance
pattern; HIGH-level sets the running disparity
to negative
RXPOL J4 input SSTL_2 signals the PHY to perform a polarity inversion
on the receive data; LOW = PHY does no
polarity inversion; HIGH = PHY does polarity
inversion
RESET_N J3 input SSTL_2 PHY reset input; active LOW
PWRDWN0 H6 input SSTL_2 transceiver power-up and power-down inputs
(see
Table 13); 0x2 = reset state
PWRDWN1 J6 input SSTL_2
