PX1011A_PX1012A_2 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 02 — 18 May 2006 20 of 32
Philips Semiconductors
PX1011A/PX1012A
PCI Express stand-alone X1 PHY
11. Characteristics
Table 18. PCI Express PHY characteristics
Symbol Parameter Conditions Min Typ Max Unit
Supplies
V
DDD1
digital supply voltage 1 for JTAG I/O 3.0 3.3 3.6 V
V
DDD2
digital supply voltage 2 for SSTL_2
I/O
2.3 2.5 2.7 V
V
DDD3
digital supply voltage 3 for core 1.2 1.25 1.3 V
V
DD
supply voltage for high-speed
serial I/O and
PVT
1.15 1.2 1.25 V
V
DDA1
analog supply voltage 1 for serializer 1.2 1.25 1.3 V
V
DDA2
analog supply voltage 2 for serializer 3.0 3.3 3.6 V
I
DDD1
digital supply current 1 for I/O 0.1 1 2 mA
I
DDD2
digital supply current 2 for SSTL_2;
no load
10 18 25 mA
I
DDD3
digital supply current 3 for core 5 10 15 mA
I
DD
supply current for high-speed
serial I/O and
PVT
15 20 25 mA
I
DDA1
analog supply current 1 for serializer 15 20 25 mA
I
DDA2
analog supply current 2 for serializer 7 10 15 mA
Receiver
UI unit interval 399.88 400 400.12 ps
V
RX_DIFFp-p
differential input peak-to-peak voltage 0.175 - 1.2 V
t
RX_MAX_JITTER
maximum receiver jitter time - - 0.6 UI
V
IDLE_DET_DIFFp-p
electrical idle detect threshold 65 - 175 mV
Z
RX_DC
DC input impedance 40 50 60 Ω
Z
RX_HIGH_IMP_DC
powered-down DC input impedance 200 - - kΩ
RL
RX_DIFF
differential return loss 15 - - dB
RL
RX_CM
common mode return loss 6 - - dB
f
clk(ref)
reference clock frequency 99.97 100 100.03 MHz
∆f
mod(clk)(ref)
reference clock modulation frequency range −0.5 - +0 %
f
mod(clk)(ref)
reference clock modulation frequency 30 - 33 kHz
V
IH(se)REFCLK
REFCLK single-end HIGH-level input voltage - 0.7 - V
V
IL(se)REFCLK
REFCLK single-end LOW-level input voltage - 0 - V
t
lock(CDR)(ref)
CDR lock time (reference loop) - - 50 µs
t
lock(CDR)(data)
CDR lock time (data loop) - - 2.5 µs
t
RX_latency
receiver latency 1 clock cycle
is 4 ns
6 - 13 clock
cycle