PCA24S08_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 11 May 2010 10 of 25
NXP Semiconductors
PCA24S08
1024 × 8-bit CMOS EEPROM with access protection
6.4.2.1 Block 0 write protection bits
The PCA24S08 provides a mechanism to divide block 0 into eight 128-bit (16-byte) pages
that can be individually protected against writes. These eight write protection (WPN) bits
are stored within a byte of the access protection page and are organized such that the
LSB protects the first 128 bits, and so on. If a bit in this byte is set to a one and the PB0
field is set to 11b, then writes are permitted on the page corresponding to the WPNx bit. If
the WPNx bit is set to a logic 0 or the PB0 is any value other than 11b, then writes are not
permitted in that page.
The write protection hierarchy for serial accesses is shown in Figure 10
. In this drawing
the bits within the boxes to the left of the arrows are the only thing that determine whether
or not the bit in the box to the right of the arrow can be written. Read access control is not
shown in this diagram. Addresses listed in this diagram are for the serial port assuming
that the R/W
bit in the command byte is set to ‘0’.
Fig 10. Write protection example
Page 0
16 bytes
Page 1
16 bytes
Page 7
16 bytes
Block 1
128 bytes
A800
A80F
A810
A81F
A870
A87F
A880
WP
Block 0
A8FF
WPN0
WPN1
WPN7
PBAPSBAP
PB0SB0
PB1SB1
Block 7
128 bytes
AE80
AEFF
PB7SB7
SB0 PB0 B800
SB1 PB1 B801
SB7 PB7 B807
SBAP PBAP B808
7 bytes
ID page
16 bytes
B809
B80F
B810
B81F
SB1
SB0
SB7
PBAPSBAP
Access
Protection
Page
PCA24S08_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 11 May 2010 11 of 25
NXP Semiconductors
PCA24S08
1024 × 8-bit CMOS EEPROM with access protection
For example, when SB1 is a 1, the PB1 field can be written to any value by the system.
When the PB1 field is 11b, Block 1 can be written to by the system. Note that the state of
the SB1 bit does not affect whether or not Block 1 can be written.
There is no individual page write protection for any other block other than block 0 within
the device. Within the remaining blocks on the chip, access permissions are controlled on
a block basis (BP bits) or full chip basis (WP pin) only.
6.4.2.2 Access Protection Page (APP)
The serial port may be used to read and write the Access Protection Page (APP) and
ID Page using device access codes B8h and B9h instead of the normal value of A8h
through AFh (hex) that are used to access the rest of the EEPROM memory. The second
byte of write commands (the word address) should be in the range of 00h through 0Fh for
the APP page and 10h through 1Fh for the ID page. This coding is shown in Figure 11
.
Reads and writes to these two pages may take place on a single byte basis only.
Multi-byte operations will be NACKed.
As an example, the bit encoding for a single byte read and write command are shown in
Figure 11
.
The PCA24S08 will acknowledge all device addresses of B8h or B9h. If the most
significant three its of the word address are not all 0 (indicating an address outside the
Access protection and ID pages), the chip will NACK the access.
Byte 0 through byte 7 of the APP contain 8 identical sets of access control fields (PBx and
SBx) for each of the eight blocks of memory on the chip, which operate according to
Table 4
. When the sticky bit in one of these bytes is set, that byte can be written by the
system. Once a sticky bit is reset (written to zero) by the software, the byte containing it
can no longer be modified by the software until the next power cycle. These bytes can
always be read by the system.
Byte 8 contains another PB field (PBAP) as bit 0 and bit 1, and an additional sticky bit
(SBAP) as bit 7. The value of the PBAP bits controls read and write access to the last
7 bytes (byte 9 through byte 15) of the APP and all 16 bytes of the ID page according to
the encoding listed in Section 6.4
. The value of the PBAP bits can only be changed, a
write from the serial port, when SBAP is HIGH. This byte can always be read by the
system. Bit 0 through bit 6 of this byte are stored in EEPROM memory and do not change
when the power is cycled or the PROT
pin changes state.
Byte 9 contains the eight block 0 write protection bits (WPN) for each page within block 0.
Byte 10 emulates a coil detection feature to keep compatibility with existing software
controlling device.
Even though the PCA24S08 does not have the RFID capability of the AT24RF03C, it
gives a ‘coil non-detected’ information when the detection feature is initiated.
The detection feature uses the Detection Enable bit (DE) and the Detect Coil bit (DC). At
power-up, DE = 0 and DC = 1. Detection is enabled by setting DE bit at 1. Since no coil is
detected, DC is then automatically reset and equal to 0.
DE is a read/write bit; DC is a read-only bit. Attempts to write to this bit will be ignored.
PCA24S08_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 11 May 2010 12 of 25
NXP Semiconductors
PCA24S08
1024 × 8-bit CMOS EEPROM with access protection
Bit 0 in the same byte emulates a TAMPER bit and is always equal to 0. TAMPER is a
read-only bit. Attempt to write a ‘1’ to this bit will be ignored.
Byte 11 through byte 14 are currently reserved and should not be used by the system.
Byte 14 may not be written by the device at any time.
Byte 11 to byte 13 are read/write bytes that are stored in the EEPROM.
Byte 14 is a read-only byte and the returned value during a read operation is FFh. A write
on it is acknowledged, but the write will be ignored.
Byte 15 contains device revision information stored in the EEPROM. It is set at the wafer
production facility and cannot be changed in the field, so any write to this byte will be
ignored but acknowledged. The value of this byte is 10h.
The memory map for the Access Protection Page is shown in Table 5 “
APP memory map.
In this table, an ‘X’ means that the value is a ‘Don’t care’ upon writing, and that it is
undefined upon reading. The PBx fields are all 2 bits wide, and the Device Revision field
is 8 bits wide. All other fields are 1 bit wide.
With the exception of the 9 Sticky Bits (SB), the two coil detect bits (DE and DC), the
tamper bit (TAMPER), and bytes 14 and 15, all bits within the Access Protection Page are
stored in EEPROM memory. Their state does not change if power is removed or when the
PROT
pin is held LOW.
The following page of memory (accessed with A4 = 1) emulate the ID field that would be
transmitted by the device from the RFID port. Bytes within it are accessed with the
address byte at B8h or B9h (write/read). Reading and writing to this page is permitted
when PBAP is 11.
a. Write operations
b. Read operations
Fig 11. Device access examples
01110001 0 0 P0A3A2A1A00
002aae8
43
D6 D5 D4 D3 D2 D1 D0D7
P0 is used to distinguish between
the APP and RFID pages:
0 = APP pages
1 = RFID pages
01110011
002aae844
D6 D5 D4 D3 D2 D1 D0D7

PCA24S08D,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC EEPROM 8K I2C 400KHZ 8SO
Lifecycle:
New from this manufacturer.
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