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PCA24S08D,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
PCA24S08_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 11 May 2010 7 of 25
NXP Semiconductors
PCA24S08
1024 × 8-bit CMOS EEPROM with access protection
6.3 Read operations
Read operations are initiated in the same manner as write operations with the exception
that the LSB of the slave address is set to logic 1.
The lower 7 bits of the word address are incremented after each transmission of a data
byte during a read. The three MSBs of the word address are not changed when the word
counter overflows. Thus, the word address overflows from 127 to 0, and from 255 to 128.
After the read of the last byte within a block, the internal serial address wraps around to
point at the beginning of that block.
Fig 7. Page write operation (16 bytes)
0 1 0 1 B2 B1 0 AS 1 A
START condition
R/W acknowledge
from slave
acknowledge
from slave
word address
A
acknowledge
from slave
word
address
P2 P1 P0 A3 A2 A1 A0B0 DATA A
acknowledge
from slave
DATA + 1
auto-increment
word address
auto-increment
word address
(cont.)
(cont.)
P
STOP condition
A
acknowledge
from slave
DATA + 15
auto-increment
word address
last byte
002aae7
92
Fig 8. Master reads PCA24S08 slave after setting word address (write word address: read data); sequential read
0 1 0 1 B2 B1 0 AS 1 A
START condition
R/W acknowledge
from slave
acknowledge
from slave
word address
second part
word address
first part
P2 P1 P0 A3 A2 A1 A0B0
DATA
(cont.)
(cont.)
P
STOP condition
A
no acknowledge
from master
DATA
auto-increment
word address
last byte
002aae793
S
ReSTART
condition
0101XX11
R/W
A
at this moment master transmitter becomes
master receiver and EEPROM slave transmitter
n bytes
A
auto-increment
word address
acknowledge
from master
acknowledge
from master
PCA24S08_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 11 May 2010 8 of 25
NXP Semiconductors
PCA24S08
1024 × 8-bit CMOS EEPROM with access protection
6.4 Access protection
Write operation on the Access protection registers can be performed when WP pin is
LOW. If the WP pin is HIGH, all write operations are prohibited from the serial port,
although write commands may be used to set the address for a subsequent read
command.
All access protection bits are stored on a separate page of the EEPROM that is not
accessed using the normal commands of a PCA24S08 memory. See Section 6.4.2.2
“Access Protection Page (APP)” for more detail on this information.
6.4.1 RFID access fields (RF)
Even though the PCA24S08 does not have the RFID capability, RFID access fields (RF)
can be stored in order to keep existing software compatibility. The fields are stored in the
EEPROM and organized as shown in Table 3
.
6.4.2 Protection Bits (PB)
The protection bits fields in the Access Protection Page determine what type of accesses
will be permitted via the serial port for each of the blocks on the chip. If an illegal access is
attempted, the command will be NACKed. The MSB (if clear) prohibits all access to the
block, and the LSB (if clear) prohibits writes. The fields are stored in the EEPROM and are
organized as shown in Table 4
.
Fig 9. Master read PCA24S08 immediately after first byte (read mode); current address read
0101XX1AS 1
START condition
R/W
acknowledge
from slave
DATA P
STOP condition
A
no acknowledge
from master
DATA
auto-increment
word address
last byte
002aae794
n bytes
A
auto-increment
word address
acknowledge
from master
Table 3. RFID access field organization
MSB LSB Function
0 0 no accesses permitted from RFID port
0 1 no accesses permitted from RFID port
1 0 read only from RFID port
1 1 no restrictions for RFID accesses
Table 4. PB organization
MSB LSB Function
0 0 no accesses permitted in the block
0 1 no accesses permitted in the block
1 0 read only; writes cause a NACK
1 1 read/write; no access constraints for data within this block
PCA24S08_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 11 May 2010 9 of 25
NXP Semiconductors
PCA24S08
1024 × 8-bit CMOS EEPROM with access protection
Accessed within the Access Protection Page is an individual CMOS Sticky Bit (SB) for
each of the 8 blocks on the device. When the value of the sticky bit is ‘0’, the Protection
Bits (PB) for the corresponding block may not be changed via the software. These bits are
all set to logic 1 when power is initially applied or when the PROT
pin is LOW. These
sticky bits may be written only to a ‘0’ via the serial interface using the standard serial write
operations. Reading the sticky bits does not affect their state.
Because permissions are set individually for each of the blocks, all reads via serial port
will only read bytes within the block that was specified when the current address was
latched in the device (with a write command). The block address bits (B2 or B1) that are
sent with the write command are ignored on a read command.
When a sticky bit is cleared (programmed at 0), the byte containing the sticky bit cannot
be changed anymore. If a write operation to this byte is attempted, it will be normally
acknowledged but no change will happen in the byte value. The device does not go to an
E/W cycle and can be accessed immediately.
If a block is protected and only read operation is allowed (the corresponding APP register
has its PB bits programmed to 10b), a write operation to this block is not acknowledged
(Slave Address and Register pointer only are acknowledged). The device does not go to
an E/W cycle and can be accessed immediately.
S – Addr+W – ACK – Reg Pointer – ACK – Data – NACK
This applies to:
• EEPROM block 0 to block 7, controlled by PB0 to PB7.
• The last 7 bytes of the APP block (09h to 0Fh) and the ID page (10h to 1Fh) controlled
by PBAP.
If a block is protected and neither read operation nor write operation is allowed (the
corresponding APP register has its PB bits programmed to 00b or 01b), a write operation
to this block is not acknowledged (Slave Address and Register pointer only are
acknowledged).
S – Addr+W – ACK – Reg Pointer – ACK – Data – NACK
A read operation to this block is not allowed.
S – Addr+W – ACK – Reg Pointer – ACK – Sr – Addr+R – NACK
S – Addr+W – ACK – Reg Pointer – ACK – P – S – Addr+R – NACK
This applies to:
• EEPROM block 0 to block 7, controlled by PB0 to PB7.
• The last 7 bytes of the APP block (09h to 0Fh) and the ID page (10h to 1Fh) controlled
by PBAP.
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PCA24S08D,118

Mfr. #:
Buy PCA24S08D,118
Manufacturer:
NXP Semiconductors
Description:
IC EEPROM 8K I2C 400KHZ 8SO
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New from this manufacturer.
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