PCA24S08_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 11 May 2010 13 of 25
NXP Semiconductors
PCA24S08
1024 × 8-bit CMOS EEPROM with access protection
6.5 PROT pin
The PROT pin is used as a power good signal. When this pin is held LOW, the serial port
is held in reset and all sticky bits are set to one. When HIGH, activity on the serial bus is
permitted and sticky bits can be set to their values.
6.6 Serial EEPROM exceptions
In general, the two-wire serial interface on the PCA24S08 functions identically to the
24C08. The following exceptions exist, as noted elsewhere in this document.
• Pins 1, 2, and 3 have different usage.
• Access to various blocks may be restricted via the access protection circuitry.
• The two block address bits (B2 and B1) in the command byte are ignored with all read
commands. They are set only via the write command.
• Multi-byte reads do not cross block boundaries, but instead wrap to the beginning of
the block.
• The serial port will be reset whenever the PROT pin is LOW.
• If more than 16 bytes are written to the EEPROM with a page write, overlapping bytes
will have their values corrupted.
• If V
DD
is 0 V, the device draws current on the SDA, SCL, WP, and PROT pins when
they are brought above 0 V.
Table 5. APP memory map
X = ‘Don’t care’ upon writing and undefined upon reading.
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 SB0 X RF0 X X PB0
1 SB1 X RF1 X X PB1
2 SB2 X RF2 X X PB2
3 SB3 X RF3 X X PB3
4 SB4 X RF4 X X PB4
5 SB5 X RF5 X X PB5
6 SB6 X RF6 X X PB6
7 SB7 X RF7 X X PB7
8 SBAP X X X X X PBAP
9 WPN7 WPN6 WPN5 WPN4 WPN3 WPN2 WPN1 WPN0
10 DE DC X X X X X TAMPER
11 reserved; R/W
12 reserved; R/W
13 reserved; R/W
14 reserved; read-only
15 device revision
