AMIS30543DBGEVB Datasheet AMIS30543C5431RG, AMIS30543DBGEVB | P25-P27

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Figure 10. Translator Table: Circular and Square

Start = 0

Step 1

Step 2

Step 3

1/4

micro step

Start = 0

Step 1

Step 2

Step 3

Uncompensated

half step

Start = 0

Step 1

Step 2

Compensated

half step

Step 3

Start = 0

Step 1

Uncompensated

full step

Step 2

Step 3

Start = 0

Step 1

Compensated full

step, 1 phase on

Step 2

Step 3

Start = 0

Step 1

Compensated full

step, 2 phase on

Step 2

Step 3

Direction

The direction of rotation is selected by means of following

combination of the DIR input pin and the SPI−controlled

direction bit <DIRCTRL>. (see Table 12 SPI Control

Parameter Overview)

NXT Input

Changes on the NXT input will move the motor current

one step up/down in the translator table (even when the

motor is disabled: <MOTEN> = 0). Depending on the

NXT−polarity bit <NXTP> (see Table 12 SPI Control

Parameter Overview), the next step is initiated either on the

rising edge or the falling edge of the NXT input.

Translator Position

The translator position MSP[8:0] can be read in SPI Status

SR4). This is a 9−bit number equivalent to the 1/128

micro−step (see Table 9 “Circular Translator Table”). The

translator position is updated immediately following a NXT

trigger.

NXT

Update

Translator Position

Update

Translator Position

Figure 11. Translator Position Timing Diagram

Synchronization of Step Mode and NXT Input

When step mode is re−programmed to another resolution

(Figure 12), then this is put in effect immediately upon the

first arriving “NXT” input. If the micro−stepping resolution

is increased, the coil currents will be regulated to the nearest

micro−step, according to the fixed grid of the increased

resolution. If however the micro−stepping resolution is

decreased, then it is possible to introduce an offset (or phase

shift) in the micro−step translator table.

If the step resolution is decreased at a translator table

position that is shared both by the old and new resolution

setting, then the offset is zero and micro−stepping is

proceeds according to the translator table.

If the translator position is not

shared both by the old and

new resolution setting, then the micro−stepping proceeds

with an offset relative to the translator table (See Figure 12

right hand side).

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DIR

NXT1

NXT2

NXT3

NXT4

Halfstep

endpos

1/4

step

Change from lower to higher resolution

startpos

PC20070604.6

DIR

NXT1

NXT2

NXT3

DIR

endpos

Halfstep

1/8

step

Change from higher to lower resolution

startpos

Figure 12. NXT−Step Mode Synchronization

Left: Change from lower to higher resolution. The left−hand side depicts the ending half−step position during which a new

step mode resolution was programmed. The right−hand side diagram shows the effect of subsequent NXT commands on the

micro−step position.

Right: Change from higher to lower resolution. The left−hand side depicts the ending micro−step position during which a new

step mode resolution was programmed. The right−hand side diagram shows the effect of subsequent NXT commands on the

half−step position.

Note: It is advised to reduce the micro−stepping resolution only at micro−step positions that overlap with desired micro−step

positions of the new resolution.

Programmable Peak−Current

The amplitude of the current waveform in the motor coils

(coil peak current = I

max

) is adjusted by means of an SPI

parameter “CUR[4:0]” (see Table 12 SPI Control Parameter

Overview). Whenever this parameter is changed, the

coil−currents will be updated immediately at the next PWM

period. Figure 13 presents the Peak−Current and Current

Ratings in conjunction to the Current setting CUR[4:0].

2 9 15 250 CUR[4:0]

Peak Current

Current Range 0

CUR[4:0] = 0 −> 2

Current Range 1

CUR[4:0] = 3 −> 9

Current Range 2

CUR[4:0] = 10 −> 15

Current Range 3

CUR[4:0] = 16 −> 25

3090 mA

Figure 13. Programmable Peak−Current Overview

1205 mA

680 mA

305 mA

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Speed and Load Angle Output

The SLA−pin provides an output voltage that indicates the

level of the Back−e.m.f. voltage of the motor. This

Back−e.m.f. voltage is sampled during every so−called ”coil

current zero crossings”. Per coil, two zero−current positions

exist per electrical period, yielding in total four zero−current

observation points per electrical period.

BEMF

ZOOM

COIL

Voltage Transient

Micro−step

Coil Current Zero Crossing

Current Decay

Zero Current

COIL

BEMF

Figure 14. Principle of Bemf Measurement

Because of the relatively high recirculation currents in the

coil during current decay, the coil voltage V

COIL

shows a

transient behavior. As this transient is not always desired in

application software, two operating modes can be selected

by means of the bit <SLAT> (see “SLA−transparency” in

Table 12 SPI Control Parameter Overview). The SLA pin

shows in “transparent mode” full visibility of the voltage

transient behavior. This allows a sanity−check of the

speed−setting versus motor operation and characteristics

and supply voltage levels. If the bit “SLAT” is cleared, then

only the voltage samples at the end of each coil current zero

crossing are visible on the SLA−pin. Because the transient

behavior of the coil voltage is not visible anymore, this mode

generates smoother Back e.m.f. input for post−processing,

e.g. by software.

In order to bring the sampled Back e.m.f. to a descent

output level (0 V to 5 V), the sampled coil voltage V

COIL

divided by 2 or by 4. This divider is set through an SPI bit

<SLAG>. (see Table 12 SPI Control Parameter Overview)

The following drawing illustrates the operation of the

SLA−pin and the transparency−bit. “PWMsh” and “I

COIL

0” are internal signals that define together with SLAT the

sampling and hold moments of the coil voltage.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P38

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DAUGHTER BOARD BIP STEP MOTOR

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