OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AMIS30543DBGEVB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38
AMIS−30543
http://onsemi.com
31
SPI INTERFACE
The serial peripheral interface (SPI) allows an external
microcontroller (Master) to communicate with
AMIS−30543. The implemented SPI block is designed to
interface directly with numerous micro−controllers from
several manufacturers. AMIS−30543 acts always as a Slave
and can’t initiate any transmission. The operation of the
device is configured and controlled by means of SPI
registers which are observable for read and/or write from the
Master.
SPI Transfer Format and Pin Signals
During a SPI transfer, data is simultaneously transmitted
(shifted out serially) and received (shifted in serially). A
serial clock line (CLK) synchronizes shifting and sampling
of the information on the two serial data lines (DO and DI).
DO signal is the output from the Slave (AMIS−30543), and
DI signal is the output from the Master. A chip select line
(CS
) allows individual selection of a Slave SPI device in a
multiple−slave system. The CS
line is active low. If
AMIS−30543 is not selected, DO is pulled up with the
external pull up resistor. Since AMIS−30543 operates as a
Slave in MODE 0 (CPOL = 0; CPHA = 0) it always clocks
data out on the falling edge and samples data in on rising
edge of clock. The Master SPI port must be configured in
MODE 0 too, to match this operation. The SPI clock idles
low between the transferred bytes.
The diagram below is both a Master and a Slave timing
diagram since CLK, DO and DI pins are directly connected
between the Master and the Slave.
DI MSB
CLK
1 2 3 4 5 6 7 8
CS
DO
# CLK cycle
MSB
LSB
LSB
6
543
21
6
543
21
Figure 18. Timing Diagram of a SPI Transfer
NOTE: At the falling edge of the eight clock pulse the data−out shift register is updated with the content of the addressed internal SPI
register. The internal SPI registers are updated at the first rising edge of the AMIS−30543 system clock when CS
= High
Transfer Packet:
Serial data transfer is assumed to follow MSB first rule.
The transfer packet contains one or more bytes.
LSB
DataCommand and SPI Register Address
CMD2 CMD1 CMD0 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 D7 D6 D5 D4 D3 D2 D1 D0
MSBLSBMSB
BYTE 1 BYTE 2
Command
SPI Register Address
Figure 19. SPI Transfer Packet
Byte 1 contains the Command and the SPI Register
Address and indicates to AMIS−30543 the chosen type of
operation and addressed register. Byte 2 contains data, or
sent from the Master in a WRITE operation, or received
from AMIS−30543 in a READ operation.
AMIS−30543
http://onsemi.com
32
Two command types can be distinguished in the
communication between master and AMIS−30543:
• READ from SPI Register with address ADDR[4:0]:
CMD2 = “0”
• WRITE to SPI Register with address ADDR[4:0]:
CMD2 = “1”
READ Operation
If the Master wants to read data from Status or Control
Registers, it initiates the communication by sending a
READ command. This READ command contains the
address of the SPI register to be read out. At the falling edge
of the eight clock pulse the data−out shift register is updated
with the content of the corresponding internal SPI register.
In the next 8−bit clock pulse train this data is shifted out via
DO pin. At the same time the data shifted in from DI
(Master) should be interpreted as the following successive
command or dummy data.
CS
DO
DATA from ADDR1OLD DATA or NOT VALID
DATA DATA
DATA from previous command or
NOT VALID after POR or RESET
DI READ DATA from ADDR 1
COMMAND or DUMMY
COMMAND
Figure 20. Single READ Operation where DATA from SPI Register with Address 1 is Read by the Master
Registers are updated with internal status at the rising
edge of the internal AMIS−30543 clock when CS
= 1
All 4 Status Registers (see SPI Registers) contain 7 data
bits and a parity check bit. The most significant bit (D7)
represents a parity of D[6:0]. If the number of logical ones
in D[6:0] is odd, the parity bit D7 equals “1”. If the number
of logical ones in D[6:0] is even then the parity bit D7 equals
“0”. This simple mechanism protects against noise and
increases the consistency of the transmitted data. If a parity
check error occurs it is recommended to initiate an
additional READ command to obtain the status again.
Also the Control Registers can be read out following the
same routine. Control Registers don’t have a parity check.
The CS
line is active low and may remain low between
successive READ commands as illustrated in Figure 22.
There is however one exception. In case an error condition
is latched in one of Status Registers (see SPI Registers) the
ERR
pin is activated (See Section Error Output). This signal
flags a problem to the external microcontroller. By reading
the Status Registers information about the root cause of the
problem can be determined. After this READ operation the
Status Registers are cleared. Because the Status Registers
and ERR
pin (see SPI Registers) are only updated by the
internal system clock when the CS
line is high, the Master
should force CS
high immediately after the READ
operation. For the same reason it is recommended to keep
the CS
line high always when the SPI bus is idle.
WRITE Operation
If the Master wants to write data to a Control Register it
initiates the communication by sending a WRITE
command. This contains the address of the SPI register to
write to. The command is followed with a data byte. This
incoming data will be stored in the corresponding Control
Register after CS
goes from low to high! AMIS−30543
responds on every incoming byte by shifting out via DO the
data stored in the last received address.
It is important that the writing action (command − address
and data) to the Control Register is exactly 16 bits long. If
more or less bits are transmitted the complete transfer packet
is ignored.
A WRITE command executed for a read−only register
(e.g. Status Registers) will not affect the addressed register
and the device operation.
Because after a power−on−reset the initial address is
unknown the data shifted out via DO is not valid.
AMIS−30543
http://onsemi.com
33
DI
CS
DO
WRITE DATA to ADDR3
NEW DATA for ADDR3
OLD DATA from ADDR3OLD DATA or NOT VALID
COMMAND
DATA DATA
DATA from previous command or
NOT VALID after POR or RESET
DATA
Figure 21. Single WRITE Operation Where DATA from the Master is Written in SPI Register with Address 3
The NEW DATA is written into the corresponding
internal register at the rising edge of CS
Examples of combined READ and WRITE
Operations
In the following examples successive READ and WRITE
operations are combined. In Figure 22 the Master first reads
the status from Register at ADDR4 and at ADDR5 followed
by writing a control byte in Control Register at ADDR2.
Note that during the write command the old data of the
pointed register is returned at the moment the new data is
shifted in
DI
CS
DO
READ DATA
from ADDR4
OLD DATA
or NOT VALID
COMMAND
DATA
DATA
DATA from previous
command or NOT VALID
after POR or RESET
COMMAND
COMMAND
DATA
DATA
DATA
DATA
from ADDR4
READ DATA
from ADDR5
DATA
from ADDR5
WRITE DATA
to ADDR 2
NEW DATA
for ADDR2
OLD DATA
from ADDR2
Figure 22. 2 Successive READ Commands Followed by a WRITE Command
Registers are updated with the internal
status at the rising edge of the internal
AMIS−30543 clock when CS
= 1
The NEW DATA is written into the
corresponding internal register at
the rising edge of CS
After the write operation the Master could initiate a read
back command in order to verify the data correctly written
as illustrated in Figure 23. During reception of the READ
command the old data is returned for a second time. Only
after receiving the READ command the new data is
transmitted. This rule also applies when the master device
wants to initiate an SPI transfer to read the Status Registers.
Because the internal system clock updates the Status
Registers only when CS
line is high, the first read out byte
might represent old status information.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38

AMIS30543DBGEVB

Mfr. #:
Buy AMIS30543DBGEVB
Manufacturer:
ON Semiconductor
Description:
DAUGHTER BOARD BIP STEP MOTOR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet