EV-ADF4153ASD1Z

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

ADF4153A Data Sheet

Rev. A | Page 12 of 24

M12

INTERPOLATOR

MODULUS VALUE (MOD)

M11 M10 M3 M2

M1

0

0

..........

0 1

0 2

0

0

..........

0

1

1 3

0

0 ..........

1 0

0 4

. . ..........

.

.

.

.

. .

..........

. .

. .

. . .......... .

. .

.

1 1 ..........

1

0 0

4092

1 1

..........

1 0 1 4093

1 1

.......... 1

1 0 4094

1

0

0

0

.

.

.

1

1

1

1 1

..........

1 1 1

4095

RF R COUNTER

DIVIDE RATIO

R4 R3 R2 R1

0

0

0

0

.

.

.

1

12

1 13

1

14

1

0

0

0

1

.

.

.

1

1

1

1

0

1

1

0

.

.

.

0

0

1

1

1

0

1

0

.

.

.

1

2

3

4

.

.

.

0

1

0

1 15

P1 PRESCALER

0

4/5

1

8/9

DB18 DB17

DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7 DB6

DB5

DB4

DB3

DB2

DB1 DB0

C2 (0) C1 (1)

M1

M2

M3

M4M5

M6

M7

M8

M9

M10M11M12R1R3R4

CONTROL

BITS

12-BIT INTERPOLATOR MODULUS VALUE (MOD)

4-BIT R COUNTER

R2

MUXOUT

0

DB20 DB19

P1M1

DB23 DB22

DB21

M2M3

P3

LOAD

CONTROL

RESERVED

PRESCALER

P3

LOAD CONTROL

0

NORMAL OPERATION

1 LOAD RESYNC

M3 M2 M1 MUXOUT

0 THREE-STATE OUTPUT

DIGITAL LOCK DETECT

ANALOG LOCK DETECT

0

0

N DIVIDER OUTPUT

LOGIC HIGH

LOGIC LOW

0

1 R DIVIDER OUTPUT

1

1 FASTLOCK SWITCH

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

1

1047-018

Figure 18. R Divider Register Map (R1)

Data Sheet ADF4153A

Rev. A | Page 13 of 24

U3 POWER-DOWN

0 NORMAL OPERATION

1 POWER-DOWN

U4 LDP

0

1

24 PFD CYCLES

40 PFD CYCLES

U5 PD POLARITY

0 NEGATIVE

1 POSITIVE

U2 CP THREE-STATE

0 DISABLED

1 THREE-STATE

U1 COUNTER RESET

0 DISABLED

ENABLED1

REFERENCE

DOUBLER

U6

0 DISABLED

1 ENABLED

REFERENCE

DOUBLER

DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (1) C1 (0)

U1U2U3U4U5CP0CP1CP2U6S1S2S3S4

CONTROL

BITS

CP CURRENT

SETTING

PD POLARITY

RESYNC

LDP

POWER-

DOWN

CP

THREE-STATE

COUNTER

RESET

DB15

CP3

CP/2

S4 S3 S2 S1 RESYNC

0 1 1

0 0 2

0 1 3

. . .

. . .

. . .

1 1 13

1 0 14

1

0

0

0

.

.

.

1

1

1

0

1

1

.

.

.

0

1

1 1 15

I

CP

(mA)

CP3 CP2 CP1 CP0 3.0kΩ 4.7kΩ 10kΩ

0 0.979 0.625 0.294

0 1.958 1.250 0.588

0 2.938 1.875 0.881

0 3.917 2.500 1.175

0 4.896 3.125 1.469

0 5.875 3.750 1.763

0 6.854 4.375 2.056

0 7.833 5.000 2.350

1 0.490 0.313 0.147

1 0.979 0.625 0.294

1 1.469 0.938 0.441

1 1.958 1.250 0.588

1 2.448 1.563 0.734

1 2.938 1.875 0.881

1 3.427 2.188 1.028

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1 3.917 2.500 1.175

11047-019

Figure 19. Control Register Map (R2)

ADF4153A Data Sheet

Rev. A | Page 14 of 24

LOW SPUR MODE00000

LOW NOISE AND SPUR MODE11100

LOWEST NOISE MODE11111

DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB1

DB0

C2 (1)

C1 (1)

T1000T5T6T7T8

CONTROL

BITS

NOISE AND SPUR

MODE

DB2

0

NOISE

AND SPUR

MODE

RESERVED

RESERVED

RESERVEDDB10, DB5, DB4, DB3

NOISE AND SPUR SETTINGDB9, DB8, DB7, DB6, DB2

RESERVED0

THESE BITS MUST BE SET TO 0

FOR NORMAL OPERATION.

11047-020

Figure 20. Noise and Spur Register (R3)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

EV-ADF4153ASD1Z

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Clock & Timer Development Tools EVAL BRD

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