ADF4153A Data Sheet
Rev. A | Page 6 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CP
CPGND
AGND
AV
DD
RF
IN
A
RF
IN
B
R
SET
DV
DD
MUXOUT
LE
SDV
DD
REF
IN
DGND
CLK
DATA
V
P
ADF4153A
TOP VIEW
(Not to Scale)
1
1047-003
Figure 3. TSSOP Pin Configuration
1
1047-004
NOTES
1. THE EXPOSED PAD MUST BE
CONNECTED TO GND.
1
CPGND
2
AGND
3
AGND
4
RF
IN
B
5
RF
IN
A
13
DATA
14
LE
15
MUXOUT
12
CLK
11
SDV
DD
6AV
DD
7
AV
DD
8
REF
IN
10DGND
9
DGND
18
V
P
19
R
SET
20
CP
17
DV
DD
16
DV
DD
TOP VIEW
(Not to Scale)
ADF4153A
Figure 4. LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
TSSOP
Pin No.
LFCSP Mnemonic Description
1 19 R
SET
Connecting a resistor between R
SET
and ground sets the maximum charge pump output current.
The relationship between I
CP
and R
SET
is
where R
SET
= 4.7 kΩ and I
CPMAX
= 5 mA.
2 20 CP Charge Pump Output. When enabled, CP provides ±I
CP
to the external loop filter, which in turn
drives the external VCO.
Charge Pump Ground. This is the ground return path for the charge pump.
4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler.
5 4 RF
IN
B Complementary Input to the RF Prescaler. This pin should be decoupled to the ground plane
with a small bypass capacitor, typically 100 pF (see Figure 12).
6 5 RF
IN
A Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO.
7 6, 7 AV
DD
Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should
be placed as close as possible to this pin. AV
DD
has a value of 3 V ± 10%. AV
DD
must have the same
voltage as DV
DD
.
8 8 REF
IN
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and an equivalent input
resistance of 100 kΩ (see Figure 11). This input can be driven from a TTL or CMOS crystal oscillator,
or it can be ac-coupled.
10 11 SDV
DD
Σ-Δ Power. Decoupling capacitors to the digital ground plane should be placed as close as possible
to this pin. SDV
DD
has a value of 3 V ± 10%. SDV
DD
must have the same voltage as DV
DD
.
11 12 CLK Serial Clock Input. The serial clock is used to clock in the serial data to the registers. The data is
latched into the shift register on the CLK rising edge. This input is a high impedance CMOS input.
12 13 DATA Serial Data Input. The serial data is loaded MSB first; the two LSBs are the control bits. This input is
a high impedance CMOS input.
13 14 LE Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one
of four latches; the latch is selected using the control bits.
14 15 MUXOUT This multiplexer output allows either the RF lock detect, the scaled RF, or the scaled reference
frequency to be externally accessed.
15 16, 17 DV
DD
Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. DV
DD
has a value of 3 V ± 10%. DV
DD
must have
the same voltage as AV
DD
.
16 18 V
P
Charge Pump Power Supply. This should be greater than or equal to V
DD
. In systems where V
DD
is 3 V,
it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
N/A 21 EPAD Exposed Pad. The exposed pad must be connected to GND.
