Data Sheet ADF4153A
Rev. A | Page 21 of 24
APPLICATIONS INFORMATION
LOCAL OSCILLATOR FOR A GSM BASE STATION
TRANSMITTER
Figure 25 shows the ADF4153A being used with a VCO to
produce the local oscillator (LO) for a GSM base station
transmitter.
The reference input signal is applied to the circuit at REF
IN
and,
in this case, is terminated in 50 Ω. A 25 MHz reference is used,
which is fed directly to the PFD. To achieve 200 kHz channel
spacing, a modulus of 125 is necessary. Note that with a modulus
of 125, which is not divisible by 2, 3, or 6, subfractional spurs are
avoided. See the Spur Mechanisms section for more information.
The charge pump output of the ADF4153A drives the loop
filter.
The charge pump current is I
CP
= 5 mA. ADIsimPLL is used to
calculate the loop filter. It is designed for a loop bandwidth of
20 kHz and a phase margin of 45 degrees.
The loop filter output drives the VCO, which in turn is fed back
to the RF input of the PLL synthesizer. It also drives the RF output
terminal. A T-circuit configuration provides 50 Ω matching
between the VCO output, the RF output, and the RF
IN
terminal
of the synthesizer.
In a PLL system, it is important to know when the loop is in
lock. This is achieved by using the MUXOUT signal from the
synthesizer. The MUXOUT pin can be programmed to monitor
various internal signals in the synthesizer. One of these is the
lock detect signal.
V
DD
V
P
DV
DD
ADF4153A
V
P
22nF
82Ω
160Ω
270nF
VCO190-902T
V
CC
RF
OUT
18Ω
18Ω
18Ω
100pF
100pF
1000pF1000pF
51Ω
4.7kΩ
REF
IN
SV
DD
4
1
6 17
DV
DD
16
DV
DD
AV
DD
7 18
5
15
14
10
20 2
R
SET
MUXOUT
LOCK
DETECT
100pF
100pF
CPGND
RF
IN
A
RF
IN
B
CLK
DATA
LE
DECOUPLING CAPACITORS SHOULD BE PLACED
AS CLOSE AS POSSIBLE TO THE PINS.
CP
8
11
FREF
IN
3
DGND
9
DGND
10
DGND
2
AGND
8.2nF
100nF10µF 100nF 10µF
10pF 100nF
51Ω
SPI-COMPATIBLE SERIAL BUS
11047-025
Figure 25. Local Oscillator for a GSM Base Station Transmitter
ADF4153A Data Sheet
Rev. A | Page 22 of 24
OUTLINE DIMENSIONS
16
9
81
PIN 1
SEATING
PLANE
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX
0.20
0.09
0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 26. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeter
0.50
BSC
0.65
0.60
0.55
0.30
0.25
0.18
COMPLIANT
T
O
JEDEC STANDARDS MO-220-WGGD-1.
BOTTOM VIEWTOP VIEW
EXPOSED
PAD
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
SEATING
PLANE
0.80
0.75
0.70
0.05 MAX
0.02 NOM
0.20 REF
0.20 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
2.30
2.10 SQ
2.00
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
1
20
6
10
11
15
16
5
08-16-2010-B
Figure 27. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-20-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range Package Description Package Option
ADF4153ABCPZ 40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6
ADF4153ABCPZ-RL7 40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6
ADF4153ABRUZ 40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADF4153ABRUZ-RL7 40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP RU-16
EV-ADF4153ASD1Z Evaluation board for ADF4153A in LFCSP package
1
Z = RoHS Compliant Part.
Data Sheet ADF4153A
Rev. A | Page 23 of 24
NOTES

EV-ADF4153ASD1Z

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Clock & Timer Development Tools EVAL BRD
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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