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EV-ADF4153ASD1Z

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
Data Sheet ADF4153A
Rev. A | Page 15 of 24
N DIVIDER REGISTER, R0
With R0[1, 0] set to [0, 0], the on-chip N divider register
is programmed. Figure 17 shows the input data format for
programming this register.
9-Bit INT Value
These nine bits control what is loaded as the INT value. This is
used to determine the overall feedback division factor. It is used
in Equation 1 (see the INT, FRAC, MOD, and R Relationship
section).
12-Bit FRAC Value
These 12 bits control what is loaded as the FRAC value into
the fractional interpolator. This is part of what determines the
overall feedback division factor. It is also used in Equation 1.
The FRAC value must be less than or equal to the value loaded
into the MOD register.
Fastlock
When set to logic high, fastlock is enabled. This sets the charge
pump current to its maximum value. When set to logic low, the
charge pump current is equal to the value programmed into the
function register. Also, if MUXOUT is programmed to setting
the fastlock switch, MUXOUT is shorted to ground when the
fastlock bit is 1 and is high impedance when this bit is 0.
R DIVIDER REGISTER, R1
With R1[1, 0] set to [0, 1], the on-chip R divider register is
programmed. Figure 18
shows the input data format for
programming this register.
Load Control
When set to logic high, the value being programmed in the
modulus is not loaded into the modulus. Instead, it sets the
resync delay of the Σ-Δ. This is done to ensure phase resync
when changing frequencies. See the Phase Resync section for
more information and a worked example.
MUXOUT
The on-chip multiplexer is controlled by DB22, DB21, and
DB20 on the ADF4153A. See Figure 18 for the truth table.
Digital Lock Detect
The digital lock detect output goes high if there are 24 succes-
sive PFD cycles with an input error of less than 15 ns (for LDP
is 0, see the Control Register, R2 section for a more thorough
explanation of the LDP bit). It stays high until a new channel is
programmed or until the error at the PFD input exceeds 30 ns
for one or more cycles. If the loop bandwidth is narrow compared
to the PFD frequency, the error at the PFD inputs may drop
below 15 ns for 24 cycles around a cycle slip. Therefore, the
digital lock detect may go falsely high for a short period until
the error again exceeds 30 ns. In this case, the digital lock detect
is reliable only as a loss-of-lock detector.
Prescaler (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the INT,
FRAC, and MOD counters, determines the overall division
ratio from the RF
IN
to the PFD input.
Operating at CML levels, it takes the clock from the RF input
stage and divides it down for the counters. It is based on a
synchronous 4/5 core. When set to 4/5, the maximum RF
frequency allowed is 2 GHz. Therefore, when operating the
ADF4153A above 2 GHz, this must be set to 8/9. The prescaler
limits the INT value.
With P = 4/5, N
MIN
= 31.
With P = 8/9, N
MIN
= 91.
4-Bit R Counter
The 4-bit R counter allows the input reference frequency
(REF
IN
) to be divided down to produce the reference clock
to the phase frequency detector (PFD). Division ratios from
1 to 15 are allowed.
12-Bit Interpolator MOD Value
These programmable bits set the fractional modulus. This is the
ratio of the PFD frequency to the channel step resolution on the
RF output. Refer to the RF Synthesizer: A Worked Example
section for more information.
The ADF4153A programmable modulus is double buffered.
This means that two events have to occur before the part uses
a new modulus value. First, the new modulus value is latched
into the device by writing to the R divider register. Second,
a new write must be performed on the N divider register.
Therefore, any time that the modulus value has been updated,
the N divider register must then be written to in order to ensure
that the modulus value is loaded correctly.
CONTROL REGISTER, R2
With R2[1, 0] set to [1, 0], the on-chip control register
is programmed. Figure 19 shows the input data format for
programming this register.
RF Counter Reset
DB2 is the RF counter reset bit for the ADF4153A. When this
is 1, the RF synthesizer counters are held in reset. For normal
operation, this bit should be 0.
RF Charge Pump Three-State
DB3 puts the charge pump into three-state mode when
programmed to 1. It should be set to 0 for normal operation.
ADF4153A Data Sheet
Rev. A | Page 16 of 24
RF Power-Down
DB4 on the ADF4153A provides the programmable power-
down mode. Setting this bit to 1 performs a power-down.
Setting this bit to 0 returns the synthesizer to normal operation.
While in software power-down mode, the part retains all
information in its registers. Only when supplies are removed
are the register contents lost.
When a power-down is activated, the following events occur:
1. All active dc current paths are removed.
2. The synthesizer counters are forced to their load state
conditions.
3. The charge pump is forced into three-state mode.
4. The digital lock detect circuitry is reset.
5. The RF
IN
input is debiased.
6. The input register remains active and capable of loading
and latching data.
Lock Detect Precision (LDP)
When DB5 is programmed to 0, 24 consecutive PFD cycles of
15 ns must occur before digital lock detect is set. When this bit
is programmed to 1, 40 consecutive reference cycles of 15 ns
must occur before digital lock detect is set.
Phase Detector Polarity
DB6 in the ADF4153A sets the phase detector polarity. When
the VCO characteristics are positive, this should be set to 1.
When they are negative, it should be set to 0.
Charge Pump Current Setting
DB7, DB8, DB9, and DB10 set the charge pump current setting.
This should be set to the charge pump current that the loop
filter is designed with (see Figure 19).
REF
IN
Doubler
Setting DB11 to 0 feeds the REF
IN
signal directly to the 4-bit RF
R counter, disabling the doubler. Setting this bit to 1 multiplies
the REF
IN
frequency by a factor of 2 before feeding into the 4-bit
R counter. When the doubler is disabled, the REF
IN
falling edge
is the active edge at the PFD input to the fractional synthesizer.
When the doubler is enabled, both the rising and falling edges
of REF
IN
become active edges at the PFD input.
When the doubler is enabled and the lowest spur mode is chosen,
the in-band phase noise performance is sensitive to the REF
IN
duty cycle. The phase noise degradation can be as much as 5 dB
for the REF
IN
duty cycles outside a 45% to 55% range. The phase
noise is insensitive to the REF
IN
duty cycle in the lowest noise
mode and in the lowest noise and spur mode. The phase noise
is insensitive to REF
IN
duty cycle when the doubler is disabled.
The maximum allowed REF
IN
frequency when the doubler is
enabled is 30 MHz.
NOISE AND SPUR REGISTER, R3
With R3[1, 0] set to [1, 1], the on-chip noise and spur register
is programmed. Figure 20 shows the input data format for
programming this register.
Noise and Spur Mode
Noise and spur mode lets the user optimize a design either for
improved spurious performance or for improved phase noise
performance. When the low spur setting is chosen, dither is
enabled. This randomizes the fractional quantization noise so
that it resembles white noise rather than spurious noise. As a
result, the part is optimized for improved spurious perfor-
mance. This operation would normally be used when the PLL
closed-loop bandwidth is wide, for fast-locking applications.
(Wide-loop bandwidth is seen as a loop bandwidth greater than
1/10 of the RF
OUT
channel step resolution (f
RES
).) A wide-loop
filter does not attenuate the spurs to the same level as a narrow-
loop bandwidth.
When the low noise and spur setting is enabled, dither is disabled.
This optimizes the synthesizer to operate with improved noise
performance. However, the spurious performance is degraded
in this mode compared to the low spur setting.
To further improve noise performance, the lowest noise setting
option can be used, which reduces the phase noise. As well as
disabling the dither, it also ensures that the charge pump is
operating in an optimum region for noise performance. This
setting is extremely useful where a narrow-loop filter band-
width is available. The synthesizer ensures extremely low noise
and the filter attenuates the spurs. The typical performance
characteristics give the user an idea of the trade-off in a typical
W-CDMA setup for the different noise and spur settings.
RESERVED BITS
These bits should be set to 0 for normal operation.
Data Sheet ADF4153A
Rev. A | Page 17 of 24
INITIALIZATION SEQUENCE
The following initialization sequence should be followed upon
powering up the part:
1. Write all zeros to the noise and spur register. This ensures
that all test modes are cleared.
2. Write again to the noise and spur register, this time
selecting which noise and spur mode is required. For
example, writing Hexadecimal 0003C7 to the part selects
lowest noise mode.
3. Enable the counter reset in the control register by writing a
1 to DB2; also select the required settings in the control
register. If using the phase resync function, set the resync
bits to the required settings.
4. Load the R divider register (with load control DB23
set to 0).
5. Load the N divider register.
6. Disable the counter reset by writing a 0 to DB2 in the
control register.
The part now locks to the set frequency.
If using the phase resync function, an extra step is needed after
Step 3. This involves loading the R divider register with load
control = 1 and the required delay interval in place of the MOD
value. The previous sequence can then be followed, ensuring
that in Step 4 the value of MOD is written to the R divider
register with load control = 0.
See the Spur Consistency and Phase Resync sections for more
information on the phase resync feature.
RF SYNTHESIZER: A WORKED EXAMPLE
The following equation governs how the synthesizer is
programmed:
RF
OUT
= [INT + (FRAC/MOD)] × [F
PFD
] (3)
where:
RF
OUT
is the RF frequency output.
INT is the integer division factor.
FRAC is the fractionality.
MOD is the modulus.
The PFD frequency is given by:
F
PFD
= [REF
IN
× (1 + D)/R] (4)
where:
REF
IN
is the reference frequency input.
D is the RF REF
IN
doubler bit.
R is the RF reference division factor.
For example, in a GSM 1800 system, where 1.8 GHz RF
frequency output (RF
OUT
) is required, a 13 MHz reference
frequency input (REF
IN
) is available and a 200 kHz channel
resolution (f
RES
) is required on the RF output. With REF
IN
doubler (D) set to 0 and reference division (R) set to 1, from
Equation 4:
F
PFD
= [13 MHz × (1 + 0)/1] = 13 MHz (5)
MOD = F
PFD
/f
RES
MOD = 13 MHz/200 kHz = 65
1.8 G = 13 MHz × (INT + FRAC/65)
where INT = 138; FRAC = 30 (6)
MODULUS
The choice of modulus (MOD) depends on the PFD frequency
(which depends on the available reference signal REF
IN
) and
the channel resolution (f
RES
) required at the RF output. For
example, a GSM system with 13 MHz REF
IN
sets the modulus to
65. This means that the RF output resolution (f
RES
) is the 200 kHz
(13 MHz/65) necessary for GSM. With dither off, the fractional
spur interval depends on the modulus values chosen. See Table 6
for more information.
REFERENCE DOUBLER AND REFERENCE DIVIDER
The reference doubler on-chip allows the input reference signal
to be doubled. This is useful for increasing the PFD comparison
frequency. Making the PFD frequency higher improves the
noise performance of the system. Doubling the PFD frequency
usually improves noise performance by 3 dB. It is important to
note that the PFD cannot be operated above specified limits due
to a limitation in the speed of the Σ-Δ circuit of the N divider.
12-BIT PROGRAMMABLE MODULUS
Unlike most other fractional-N PLLs, the ADF4153A lets the
user program the modulus over a 12-bit range. This means that
the user can set up the part in many different configurations for
the application, when combined with the reference doubler and
the 4-bit R counter.
The following is an example of an application that requires
1.75 GHz RF and 200 kHz channel step resolution. The system
has a 13 MHz reference signal.
One possible setup is feeding the 13 MHz directly to the PFD
and programming the modulus to divide by 65. This results in
the required 200 kHz resolution.
Another possible setup is using the reference doubler to create
26 MHz from the 13 MHz input signal. This 26 MHz is then fed
into the PFD. The modulus is now programmed to divide by
130. This also results in 200 kHz resolution and offers superior
phase noise performance over the previous setup.
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EV-ADF4153ASD1Z

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