73S8009C Data Sheet DS_8009C_025
22 Rev. 1.5
CMDVCC
RST
CLK
I/O
VCC_ON
VCC
t1 t2 t3
t4
t5
Figure 6: Deactivation Sequence
3.7 OFF and Fault Detection
There are two different cases that the system controller can monitor the OFF signal: to query regarding
the card presence outside card sessions, or for fault detection during card sessions.
Outside a card session: In this condition, CMDVCC (#/%) are always high, OFF is low if the card is not
present, and high if the card is present. Because it is outside a card session, no fault detection can occur
and it will not act upon the OFF signal. No deactivation is required during this time.
During a card session: CMDVCC# and/or CMDVCC% is always low, and OFF falls low if the card is
extracted or if any fault detection is detected. At the same time that OFF is set low, the sequencer starts
the deactivation process and the host should stop all transitions on the signal lines.
Figure 7 shows the timing diagram for the signals CMDVCC (#/%), PRES, and OFF during a card session
and outside the card session.
PRES
OFF
CMDVCC
VCC
outside card session within card session
OFF is low by
card extracted
OFF is low by
any fault
within card
session
Figure 7: OFF Activity
DS_8009C_025 73S8009C Data Sheet
Rev. 1.5 23
3.8 Chip Selection
The CS pin allows multiple circuits to operate in parallel, driven from the same host control bus. When
CS is high, the pins RSTIN, CMDVCC%, CMDVCC# and CLKIN control the chip as described. The pins
I/OUC, AUX1UC, and AUX2UC have 11 k pull-up resistors and operate to transfer data to the smart
card via I/O, AUX1, and AUX2 when the smart card is activated. The signals OFF and RDY have 20 k
pull-up resistors.
When CS goes low, the states of the pins RSTIN, CMDVCC%, CMDVCC, and CLKIN are latched and held
internally. The pull-up for pins I/OUC, AUX1UC, and AUX2UC become a very weak pull-up of
approximately 3 µA. No transfer of data is possible between I/OUC, AUX1UC, AUX2UC and the
smart-card signals I/O, AUX1, and AUX2. The signals OFF and RDY are set to high impedance and the
internal pull-up resistors of 20 k are disconnected. With regard to de-activation, CS does not affect the
operation of the fault sensing circuits and card sense input.
CS
OFF, I/OUC,
AUX1UC, AUX2UC
CONTROL SIGNALS
FUNCTIONAL
HI-Z STATE
HI-Z STATE
t
SL
t
DZ
t
IS
t
SI
t
ID
t
DI
Figure 8: CS Timing Definitions
73S8009C Data Sheet DS_8009C_025
24 Rev. 1.5
3.9 I/O Circuitry and Timing
The states of the I/O, AUX1, and AUX2 pins are low after power on reset and they are in high when the
activation sequencer turns on the I/O reception state. See the Activation and De-activation Sequence
section for more details on when the I/O reception is enabled. The states of I/OUC, AUX1UC, and
AUX2UC are high after power on reset.
Within a card session and when the I/O reception state is turned on, the first I/O line on which a falling
edge is detected becomes the input I/O line and the other becomes the output I/O line. When the input
I/O line rising edge is detected, then both I/O lines return to their neutral state. Figure 9 shows the state
diagram of how the I/O and I/OUC lines are managed to become input or output.
Neutral
State
I/OUC
in
I/O
reception
I/OICC
in
No
Yes
No No
No
Yes
No
Yes
I/O
&
not I/OUC
I/OUC
&
not I/O
I/OUC I/O
yesyes
Figure 9: I/O and I/OUC State Diagram

73S8009C-32IMR/F

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
I/O Controller Interface IC Smart Card Interface IC
Lifecycle:
New from this manufacturer.
Delivery:
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