DS_8009C_025 73S8009C Data Sheet
Rev. 1.5 5
Figures
Figure 1: 73S8009C Block Diagram ......................................................................................................... 3
Figure 2: 73S8009C 32-Pin QFN Pinout
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Figure 3: Typical 73S8009C Application Schematic
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Figure 4: 73S8009C Logical Block Diagram
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Figure 5: Activation Sequence
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Figure 6: Deactivation Sequence
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Figure 7: OFF Activity
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Figure 8: CS Timing Definitions
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Figure 9: I/O and I/OUC State Diagram
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Figure 10: I/O – I/OUC Delays - Timing Diagram
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Figure 11: On_Off Pin
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Figure 12: Open Drain type – OFF and RDY
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Figure 13: Power Input/Output Circuit, VDD, LIN, VPC, VCC, VP
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Figure 14: Smart Card CLK Driver Circuit
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Figure 15: Smart Card RST Driver Circuit
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Figure 16: Smart Card IO, AUX1, and AUX2 Interface Circuit
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Figure 17: Smart Card I/OUC, AUX1UC and AUX2UC Interface Circuit
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Figure 18: General Input Circuit
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Figure 19: OFF_REQ Interface Circuit
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Figure 20: 32-Pin QFN Package Dimensions
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Tables
Table 1: 73S8009C Pin Definitions .......................................................................................................... 7
Table 2: Absolute Maximum Device Ratings
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Table 3: Recommended Operating Conditions
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Table 4: DC Smart Card Interface Requirements
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Table 5: Digital Signals Characteristics
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Table 6: DC Characteristics
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Table 7: Voltage / Temperature Fault Detection Circuits ......................................................................... 15
Table 8: Thermal Characteristics
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Table 9: Order Numbers and Packaging Marks
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