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73S8009C-32IMR/F

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
DS_8009C_025 73S8009C Data Sheet
Rev. 1.5 7
Table 1 describes the pin functions for the device.
Table 1: 73S8009C Pin Definitions
Pin
Name
Pin
(QFN32)
Type
Equivalent
Circuit
Description
Card Interface
I/O 22 IO Figure 16 Card I/O: Data signal to/from card. Includes a pull-up
resistor to V
CC.
AUX1 21 IO Figure 16 AUX1: Auxiliary data signal to/from card. Includes a
pull-up resistor to V
CC.
AUX2 20 IO Figure 16 AUX2: Auxiliary data signal to/from card. Includes a
pull-up resistor to V
CC.
RST 18 O Figure 15 Card reset: provides reset (RST) signal to card. RST is
the pass through signal on RSTIN. Internal control logic
will hold RST low when card is not activated or VCC is
too low.
CLK 16 O Figure 14 Card clock: provides clock signal (CLK) to card. CLK is
the pass through of the signal on pin CLKIN. Internal
control logic will hold CLK low when card is not
activated or VCC is too low.
PRES 14 I Figure 18 Card Presence switch: active high indicates card is
present. Should be tied to GND when not used, but it
Includes a high-impedance pull-down current source.
PRES 13 I Figure 18 Card Presence switch: active low indicates card is
present. Should be tied to V
DD
when not used, but it
Includes a high-impedance pull-up current source.
VCC 19 PSO Figure 13 Card power supply – logically controlled by sequencer,
output of LDO regulator. Requires an external 0.47 µF
low ESR filter capacitor to GND.
GND 17 GND – Card ground.
Miscellaneous Inputs and Outputs
CLKIN 7 I Figure 18 Clock signal source for the card clock.
TEST1 10
–
Factory test pin. This pin must be tied to GND in
typical applications.
TEST2 30
–
Factory test pin. This pin must be tied to GND in
typical applications.
Power Supply and Ground
VDD 29 PSO
Figure 13 System interface supply voltage and supply voltage for
companion controller circuitry. Requires a minimum of
two 0.1 µF capacitors to ground for proper decoupling.
VPC 26 PSI
Figure 13 Power supply source for main voltage converter circuit.
A 10 µF and a 0.1 µF ceramic capacitor must be
connected to this pin.
VBAT 25
Alternate power source input, typically from two series
cells, V > 4 V.
73S8009C Data Sheet DS_8009C_025
8 Rev. 1.5
Pin
Name
Pin
(QFN32)
Type
Equivalent
Circuit
Description
VBUS 23
Alternate power source input from USB connector or
hub.
LIN 27 PSI
Figure 13
Connection to 10 µH inductor for internal step up
converter. Note: inductor must be rated for 400 mA
maximum peak current.
VP 15 PSO
Figure 13 Intermediate output of main converter circuit. Requires
an external 4.7 µF low ESR filter capacitor to GND.
GND 28,31
– Ground.
Microcontroller Interface
CS
12
I
Figure 18
When CS = 1, the control and signal pins are configured
normally. When CS is set low, CMDVCC%, RSTIN, and
CMDVCC# are latched. I/OUC, AUX1UC, and
AUX2UC are set to high-impedance pull-up mode and
do not pass data to or from the smart card. Signals
RDY and OFF are disabled to prevent a low output and
the internal pull-up resistors are disconnected.
OFF 32 O
Figure 12
Interrupt signal to the processor. Active Low - Multi-
function indicating fault conditions and card presence.
Open drain output configuration – It includes an internal
20 kΩ pull-up to V
DD.
Pull-
up is disabled in Power down
state and CS = 0 modes.
I/OUC 1 IO Figure 17
System controller data I/O to/from the card. Includes a
pull-up resistor to V
DD.
AUX1UC 2 IO Figure 17
System controller auxiliary data I/O to/from the card.
Includes a pull-up resistor to V
DD.
AUX2UC 3 IO Figure 17
System controller auxiliary data I/O to/from the card.
Includes a pull-up resistor to V
DD.
CMDVCC%
CMDVCC#
4
5
I
I
Figure 18
Logic low on one or both of these pins will cause the
LDO to ramp the Vcc supply to the smart card and
smart card interface to the value described in the
following table.
CMDVCC% CMDVCC# Vcc Output Voltage
0 0 1.8 V
0 1 5.0 V
1 0 3.0 V
1 1 LDO Off
Note: See the description of the Card Power Supply for
more detail on the operation of CMDVCC% and
CMDVCC#.
RSTIN 6 I
Figure 18 Reset Input: This signal is the reset command to the
card.
RDY 8
Figure 12 Signal to controller indicating the 73S8009C is ready
because V
CC
is above the required value after
CMDVCC% and/or CMDVCC# is asserted low. A 20 kΩ
pull-up resistor to V
DD
is provided internally. Pull-up is
disabled in Power down state and CS=0 modes.
DS_8009C_025 73S8009C Data Sheet
Rev. 1.5 9
Pin
Name
Pin
(QFN32)
Type
Equivalent
Circuit
Description
ON_OFF 24 I
Figure 11
Power control pin. Connected to normally open SPST
switch to ground. Closing switch for duration greater
than de-
bounce period will turn 73S8009C circuit “on.”
If 73S8009C is “on,” closing switch will turn 73S8009C
to “off” state after the de-bounce period and
OFF_REQ/OFF_ACK handshake.
OFF_REQ 11 O
Figure 19
Digital output. Request to the host system controller to
turn the 73S8009C off. If ON_OFF switch is closed (to
ground) for de-bounce duration and circuit is “on,”
OFF_REQ will go high (Request to turn OFF).
Connected to OFF_ACK via 100 kΩ internal resistor.
OFF_ACK 9 I
Figure 18 Setting OFF_ACK high will power “off” all analog
functions and disconnect the 73S8009C from V
BAT
or
V
PC
. The pin has an internal 100 kΩ resistor
connection to OFF_REQ so that when not connected or
no host interaction is required, the Acknowledge will be
true and the circuit will turn “off” immediately with
OFF_REQ.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

73S8009C-32IMR/F

Mfr. #:
Buy 73S8009C-32IMR/F
Manufacturer:
Maxim Integrated
Description:
I/O Controller Interface IC Smart Card Interface IC
Lifecycle:
New from this manufacturer.
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