10
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory Industrial and Commercial Temperature Ranges
EndofbufferflagforBuffer#
EndofbufferflagforBuffer#2
15
SBHH H HHH HH HH HH H 1 0LSBI/OBITSH
3016 drw 12
Buffer #1 flow control
Buffer #2 flow control
Counter Release
(STOP Mode Only)
15
SB LSB I/O BITS
H
HHH HHH432 1 0HHHH
3016 drw 11
NOTE:
1. "H" = V
OH for I/O in the output state and "Don't Cares" for I/O in the input state.
Flow Control Register Description
(1,2)
Cases 6 and 7: Flag Status Register Bit Description
(1)
Flow Control Bits
Cases 6: Flag Status Register
Write Conditions
(1)
Case 7: Flag Status Register Read
Conditions
NOTES:
1. "H" = V
OH for I/O in the output state and "Don't Cares"' for I/O in the input state.
2. Writing a 0 into bit 4 releases the address pointer after it is stopped due to the STOP mode and allows sequential write operations to resume. This occurs asynchronously
of SCLK, and therefore caution should be taken. The pointer will be at address EOB+2 on the next rising edge of SCLK that is enabled by CNTEN. The pointer is also released
by RST, SLD, SSTRT
1 and SSTRT2 operations.
Cases 8 and 9: (Reserved)
Illegal operations. All outputs will be HIGH on the I/O bus during a READ.
NOTES:
1. EOB
1 and EOB2 may be asserted (set) at the same time, if both end addresses have been loaded with the same value.
2. CMD flow control bits are unchanged, the count does not continue advancement.
3. If EOB
1 and EOB2 are equal, then the pointer will jump to the start of Buffer #1.
4. If counter has stopped at EOBx and was released by bit 4 of the flow control register, CNTEN must be LOW on the next rising edge of SCLK otherwise the flow control will
remain in the STOP mode.
NOTES:
1. Either bit 0 or bit 1, or both bits, may be changed simultaneously. One may be
cleared while the second is left alone or cleared.
2. Remains as it was prior to the CMD operation, either HIGH (1) or LOW (0).
Flow Control
Bit 1 & Bit 0
(Bit 3 & Bit 2)
Mode
Functional Description
00 BUFFER
CHAINING
EOB
1
(EOB
2
) is asserted (active LOW output) when the pointer matches the end address of Buffer #1 (Buffer #2). The
pointer value is changed to the start address of Buffer #2 (Buffer #1)
(1,3)
01 STOP
EOB
1
(EOB
2
) is asserted when the pointer matches the end address of Buffer #1 (Buffer #2).
The address pointer will stop incrementing when it reaches the next address (EOB address + 1), if CNTEN is LOW on the
next clock's rising edge. Otherwise, the address pointer will stop incrementing on EOB. Sequential write operations are
inhibited after the address pointer is stopped. The pointer can be released by bit 4 of the flow control register.
(1,2,4)
10 LINEAR
EOB
1
(EOB
2
) is asserted when the pointer matches the end address of Buffer #1 (Buffer #2). The pointer keeps
incrementing for further operations.
(1)
11 MASK
EOB
1
(EOB
2
) is not asserted when the pointer reaches the end address of Buffer #1 (Buffer #2), although the flag status
bits will be set. The pointer keeps incrementing for further operations.
3016 tbl 17
Flag Status Bit 0, (Bit 1) Functional Description
0 Clears Buffer Flag EOB
1
, (EOB
2
).
1
No change to the Buffer Flag.
(2 )
3016 tb l 18
Flag Status Bit 0, (Bit 1) Functional Description
0
EOB
1
(EOB
2
) flag has not been set, the
pointer has not reached the end of the
buffer.
1
EOB
1
(EOB
2
) flag has been set, the
pointer has reached the end of the
buffer.
3016 tbl 19
