16
IDT70825S/L
High-Speed 8K x 16 Sequential Access Random Access Memory Industrial and Commercial Temperature Ranges
Sequential Port: Write, Pointer Load, Burst Read
NOTES:
1. If SLD = V
IL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = V
IH for the SCLK's rising edge, the internal address counter will not advance.
3. Pointer is not incremented on cycle immediately following SLD even if CNTEN is LOW.
Read STRT/EOB Flag Timing - Sequential Port
(1)
CYC
D1D0
t
CH
t
CL
t
DS
t
DH
t
OHZ
t
EH
t
ES
t
EH
t
ES
(1)
(3)
A0Dx
HIGH IMPEDANCE
t
WS
t
WH
t
WH
t
OLZ
t
CKLZ
t
WS
t
WH
t
WH
(2)
D2
t
DS
t
DH
(2)
SLD
CNTEN
SR/W
SCE
SOE
SCLK
SI/O
IN
SI/O
OUT
3016 drw 18
t
WS
t
WS
t
CD
t
SOE
CNTEN
(2)
t
OLZ
t
OHZ
D1
D2
SSTRT1/2
SR/W
SCE
SOE
SCLK
CYC
t
CH
t
CL
t
EH
t
ES
t
EH
t
ES
(4)
(1)
Dx
HIGH IMPEDANCE
t
WS
t
WH
t
WS
t
WH
t
CD
t
SOE
t
WS
t
WH
t
WS
t
WH
(2)
D3
t
DS
t
DH
D0
t
CKLZ
(3)
(5)
EOB
1/2
t
EB
SI/O
IN
SI/O
OUT
3016 drw19
NOTES: (Also used in the Figure "Read STRT/EOB Flag Timing")
1. If SSTRT
1 or SSTRT2 = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = V
IH for the SCLK's rising edge, the internal address counter will not advance.
3. SOE will control the output and should be HIGH on power-up. If SCE = V
IL and is clocked in while SR/W = VIH, the data addressed will be read out within that cycle. If SCE
= V
IL and is clocked in while SR/W = VIL, the data addressed will be written to if the last cycle was a read. SOE may be used to control the bus contention and permit a write
on this cycle.
4. Unlike SLD case, CNTEN is not disabled on cycle immediately following SSTRT.
5. If SR/W = V
IL, data would be written to D0 again since CNTEN = VIH.
6. SOE = V
IL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
