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CY28405OXC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
CK409-Compliant Clock Synthesize
r
CY28405
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07512 Rev. *B Revised June 16, 2004
Features
• Supports Intel
Springdale/Prescott (CK409)
• Selectable CPU frequencies
• 3.3V power supply
• Nine copies of PCI clock
• Four copies 3V66 clock with one optional VCH
• Two copies 48-MHz USB clock
• Two copies REF clock
• Three differential CPU clock pairs
• Dial-A-Frequency
®
• Supports SMBus/I
2
C Byte, Word, and Block Read/Write
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 48-pin SSOP package
CPU 3V66 PCI REF 48M
x 3 x 4 x 9 x 2 x 2
Block Diagram Pin Configuration
~
VDD_REF
XTAL
PLL Ref Freq
XOUT
XIN
VDD_PCI
OSC
SCLK
PLL 1
WD
Timer
VDD_48MHz
SDATA
VDD_3V66
Divider
Network
VDD_CPU
FS_[A:E]
PD#
REF[0:1]
VTT_PWRGD#
IREF
3V66_[0:2]
PCIF[0:2]
PCI[0:5]
DOT_48
3V66_3/VCH
2
PLL2
CPUT[0:1,ITP], CPUC[0:1,ITP]
USB_48
I
2
C
Logic
RESET#
SELVCH
MODE
SSOP-48
**FS_A/REF_0
**FS_B/REF_1
XIN
XOUT
VSS_REF
*FS_C/PCIF0
*FS_D/PCIF1
*FS_E/PCIF2
VDD_PCI
VSS_PCI
PCI0
PCI1
PCI2
PCI3
VDD_PCI
VSS_PCI
PCI4
PCI5
RESET#/PD#
DOT_48
USB_48
VSS_48
VDD_48
VDDA
VSSA
VDD
DNC***
DNC***
VSS
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
VSS_CPU
CPUT_ITP
CPUC_ITP
SCLK
SDATA
3V66_0
VTT_PWRGD#
IREF
VDD_3V66
3V66_2/MODE*
3V66_3/VCH/SELVCH**
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CY28405
VDD_REF
3V66_1
VSS_3V66
** 150k Internal Pull-down
* 150k Internal Pull-up
*** Do Not Connect
[+] Feedback
CY28405
Document #: 38-07512 Rev. *B Page 2 of 19
Pin Description
Pin No. Name Type Description
1, 2 REF(0:1) O, SE Reference Clock. 3.3V 14.318-MHz clock output.
1, 2, 7, 8, 9 FS_A, FS_B, FS_C,
FS_D, FS_E
I 3.3V LVTTL latched input for CPU frequency selection.
4XIN ICrystal Connection or External Reference Frequency Input. This pin
has dual functions. It can be used as an external 14.318-MHz crystal
connection or as an external reference frequency input.
5XOUT O, SECrystal Connection. Connection for an external 14.318-MHz crystal
output.
39, 42, 45 CPUT(0:1,ITP) O, DIF CPU Clock Output. Differential CPU clock outputs.
38, 41, 44 CPUC(0:1,ITP) O, DIF CPU Clock Output. Differential CPU clock outputs.
36, 35 DNC Do Not Connect.
30, 29 3V66(0:1) O, SE 66-MHz Clock Output. 3.3V 66-MHz clock from internal VCO.
25 3V66_3/VCH/SELVCH I/O, SE
PD
48- or 66-MHz Clock Output. 3.3V selectable through external SELVCH
strapping resistor and SMBus to be 66-MHz or 48-MHz. Default is 66-MHz.
0 = 66 MHz, 1 = 48 MHz
26 3V66_2/MODE I/O, SE
PU
66-MHz Clock Output. 3.3V 66-MHz clock from internal VCO. Reset or
Power-down Mode Select. Selects between RESET# output or PWRDWN#
input for the PWRDWN#/RESET# pin. Default is RESET#. 0 = PD#, 1 =
RESET
7, 8, 9 PCIF(0:2) O, SE Free Running PCI Output. 33-MHz clocks divided down from 3V66.
12, 13, 14,
15, 18, 19
PCI(0:5) O, SE PCI Clock Output. 33-MHz clocks divided down from 3V66.
22 USB_48 O, SE Fixed 48-MHz clock output.
21 DOT_48 O, SE Fixed 48-MHz clock output.
46 IREF I Current Reference. A precision resistor is attached to this pin which is
connected to the internal current reference.
20 RESET#/PD# I/O, PU 3.3V LVTTL input for Power-down# active LOW. Watchdog Timeout
Reset Output
33 VTT_PWRGD# I 3.3V LVTTL input is a level sensitive strobe used to latch the FS[A:E]
input (active LOW).
32 SDATA I/O SMBus compatible SDATA.
31 SCLK I SMBus compatible SCLOCK.
48 VDDA PWR 3.3V Power supply for PLL.
47 VSSA GND Ground for PLL.
3, 10, 16,
24, 27, 34,
40
VDD(REF,PCI,48,3V66,C
PU,ITP)
PWR 3.3V Power supply for outputs.
6, 11, 17,
23, 28, 37,
43
VSS(REF,PCI,48,3V66,
CPU,ITP)
GND Ground for outputs.
[+] Feedback
CY28405
Document #: 38-07512 Rev. *B Page 3 of 19
MODE Select
The hardware strapping MODE input pin can be used to select
the functionality of the RESET#/PD# pin. The default (internal
pull up) configuration is for this pin to function as a RESET#
Watchdog output. When pulled LOW during device power-up,
the RESET#/PD# pin will be configured to function as a Power
Down input pin.
Frequency Select Pins
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A through FS_E inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled low by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FS_A through FS_E input values. For all logic
levels of FS_A through FS_E, VTT_PWRGD# employs a
one-shot functionality in that once a valid low on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#
and FS_A through FS_E transitions will be ignored.
Table 1. Frequency Selection Table
Input Conditions Output Frequency
VCO Freq.
PLL Gear
Constants
(G)
FS_E FS_D FS_C FS_B FS_A
CPU 3V66 PCIFSEL_4 FSEL_3 FSEL_2 FSEL_1 FSEL_0
0 0 0 0 0 100.7 67.1 33.6 805.6 24004009.32
0 0 0 0 1 100.2 66.8 33.4 801.6 24004009.32
0 0 0 1 0 108.0 72.0 36.0 864.0 24004009.32
0 0 0 1 1 101.2 67.5 33.7 809.6 24004009.32
0 0 1 0 0 Reserved Reserved Reserved Reserved Reserved
0 0 1 0 1 Reserved Reserved Reserved Reserved Reserved
0 0 1 1 0 Reserved Reserved Reserved Reserved Reserved
0 0 1 1 1 Reserved Reserved Reserved Reserved Reserved
0 1 0 0 0 125.7 62.9 31.4 754.2 32005345.76
0 1 0 0 1 130.3 65.1 32.6 781.6 32005345.76
0 1 0 1 0 133.6 66.8 33.4 801.6 32005345.76
0 1 0 1 1 134.2 67.1 33.6 805.2 32005345.76
0 1 1 0 0 134.5 67.3 33.6 807.0 32005345.76
0 1 1 0 1 148.0 74.0 37.0 888.0 32005345.76
0 1 1 1 0 Reserved Reserved Reserved Reserved Reserved
0 1 1 1 1 Reserved Reserved Reserved Reserved Reserved
1 0 0 0 0 Reserved Reserved Reserved Reserved Reserved
1 0 0 0 1 Reserved Reserved Reserved Reserved Reserved
1 0 0 1 0 167.4 55.8 27.9 669.6 48008018.65
1 0 0 1 1 170.0 56.7 28.3 680.0 48008018.65
1 0 1 0 0 175.0 58.3 29.2 700.0 48008018.65
1 0 1 0 1 180.0 60.0 30.0 720.0 48008018.65
1 0 1 1 0 185.0 61.7 30.8 740.0 48008018.65
1 0 1 1 1 190.0 63.3 31.7 760.0 48008018.65
1 1 0 0 0 100.9 67.3 33.6 807.2 24004009.32
1 1 0 0 1 133.9 67.0 33.5 803.4 32005345.76
1 1 0 1 0 200.9 67.0 33.5 803.6 48008018.65
1 1 0 1 1 Reserved Reserved Reserved Reserved Reserved
1 1 1 0 0 100.0 66.7 33.3 800.0 24004009.32
1 1 1 0 1 133.3 66.7 33.3 800.0 32005345.76
1 1 1 1 0 200.0 66.7 33.3 800.0 48008018.65
1 1 1 1 1 Reserved Reserved Reserved Reserved Reserved
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P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

CY28405OXC

Mfr. #:
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Manufacturer:
Cypress Semiconductor
Description:
IC CLOCK SYNTHESIZER 48SSOP
Lifecycle:
New from this manufacturer.
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