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CY28405OXC

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CY28405
Document #: 38-07512 Rev. *B Page 4 of 19
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. The interface can also be
accessed during power-down operation.
Data Protocol
The clock driver serial protocol accepts Byte Write, Byte Read,
Block Write and Block Read operation from any external I
2
C
controller. For Block Write/Read operation, the bytes must be
accessed in sequential order from lowest to highest byte (most
significant bit first) with the ability to stop after any complete
byte has been transferred. For Byte Write and Byte Read
operations, the system controller can access individual
indexed bytes. The offset of the indexed byte is encoded in the
command code, as described in Table 2.
The Block Write and Block Read protocol is outlined in Table 3
while Table 4 outlines the corresponding Byte Write and Byte
Read protocol. The slave receiver address is 11010010 (D2h).
Table 2. Command Code Definition
Bit Description
7 0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
(6:0) Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations, these bits
should be ‘0000000’
Table 3. Block Read and Block Write Protocol
Block Write Protocol Block Read Protocol
Bit Description Bit Description
1 Start 1 Start
2:8 Slave address – 7 bits 2:8 Slave address – 7 bits
9 Write 9 Write
10 Acknowledge from slave 10 Acknowledge from slave
11:18
Command Code – 8-bit ‘00000000’ stands for
block operation
11:18
Command Code – 8-bit ‘00000000’ stands for
block operation
19 Acknowledge from slave 19 Acknowledge from slave
20:27 Byte Count – 8 bits 20 Repeat start
28 Acknowledge from slave 21:27 Slave address – 7 bits
29:36 Data byte 0 – 8 bits 28 Read
37 Acknowledge from slave 29 Acknowledge from slave
38:45 Data byte 1 – 8 bits 30:37 Byte count from slave – 8 bits
46 Acknowledge from slave 38 Acknowledge
.... Data Byte N/Slave Acknowledge... 39:46 Data byte from slave – 8 bits
.... Data Byte N – 8 bits 47 Acknowledge
.... Acknowledge from slave 48:55 Data byte from slave – 8 bits
.... Stop 56 Acknowledge
.... Data bytes from slave/Acknowledge
.... Data byte N from slave – 8 bits
.... Not Acknowledge
.... Stop
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CY28405
Document #: 38-07512 Rev. *B Page 5 of 19
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol Byte Read Protocol
Bit Description Bit Description
1Start 1Start
2:8 Slave address – 7 bits 2:8 Slave address – 7 bits
9 Write = 0 9 Write = 0
10 Acknowledge from slave 10 Acknowledge from slave
11:18 Command Code – 8 bits
‘1xxxxxxx’ stands for byte operation, bits[6:0] of
the command code represents the offset of the
byte to be accessed
11:18 Command Code – 8 bits
‘1xxxxxxx’ stands for byte operation, bits[6:0]
of the command code represents the offset of
the byte to be accessed
19 Acknowledge from slave 19 Acknowledge from slave
20:27 Data byte from master – 8 bits 20 Repeat start
28 Acknowledge from slave 21:27 Slave address – 7 bits
29 Stop 28 Read = 1
29 Acknowledge from slave
30:37 Data byte from slave – 8 bits
38 Not Acknowledge
39 Stop
Byte 0: Control Register 0
Bit @Pup Name Description
7 0 Reserved, Set= 0
6 1 PCIF
PCI
PCI Drive Strength Override
0 = Force All PCI and PCIF Outputs to Low Drive Strength
1= Force All PCI and PCIF Outputs to High Drive Strength
5 0 Reserved Reserved, Set= 0
4 HW FS_E Power up latched value of FS_E pin
3 HW FS_D Power up latched value of FS_D pin
2 HW FS_C Power up latched value of FS_C pin
1 HW FS_B Power up latched value of FS_B pin
0 HW FS_A Power up latched value of FS_A pin
Byte 1: Control Register 1
Bit @Pup Name Description
7 0 Reserved Reserved, set = 0
6 1 Reserved Reserved, set = 1
5 1 Reserved Reserved, set = 1
4 1 Reserved Reserved, set = 1
3 1 Reserved Reserved, set = 1
2 1 CPUT_ITP, CPUC_ITP CPUT/C_ITP Output Enable
0 = Disabled (three-state), 1 = Enabled
1 1 CPUT1, CPUC1 CPU(T/C)1 Output Enable,
0 = Disabled (three-state), 1 = Enabled
0 1 CPUT0, CPUC0 CPU(T/C)0 Output Enable
0 = Disabled (three-state), 1 = Enabled
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CY28405
Document #: 38-07512 Rev. *B Page 6 of 19
Byte 2: Control Register 2
Bit @Pup Name Description
7 0 Reserved Reserved, set = 0
6 0 Reserved Reserved, set = 0
5 0 CPUT_ITP, CPUC_ITP CPUT/C_ITP Pwrdwn drive mode
0 = Driven in power- down, 1 = three-state
4 0 CPUT1, CPUC1 CPU(T/C)1 Pwrdwn drive mode
0 = Driven in power-down, 1 = three-state
3 0 CPUT0, CPUC0 CPU(T/C)0 Pwrdwn drive mode
0 = Driven in power-down, 1 = three-state
2 0 Reserved Reserved
1 0 Reserved Reserved
0 0 Reserved Reserved
Byte 3: Control Register 3
Bit @Pup Name Description
7 1 SW PCI_STP Function
0= PCI_STP assert, 1= PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI and PCIF outputs will be
stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI and PCIF outputs will resume
in a synchronous manner with no short pulses.
6 1 Reserved Reserved
5 1 PCI5 PCI5 Output Enable
0 = Disabled, 1 = Enabled
4 1 PCI4 PCI4 Output Enable
0 = Disabled, 1 = Enabled
3 1 PCI3 PCI3 Output Enable
0 = Disabled, 1 = Enabled
2 1 PCI2 PCI2 Output Enable
0 = Disabled, 1 = Enabled
1 1 PCI1 PCI1 Output Enable
0 = Disabled, 1 = Enabled
0 1 PCI0 PCI0 Output Enable
0 = Disabled, 1 = Enabled
Byte 4: Control Register 4
Bit @Pup Name Description
7 0 USB_48 USB 48 Drive Strength Control
0 = High Drive Strength, 1 = Low Drive Strength
6 1 USB_48 USB_48 Output Enable
0 = Disabled, 1 = Enabled
5 0 PCIF2 Allow control of PCIF2 with assertion of SW PCI_STP
0 = Free Running, 1 = Stopped with SW PCI_STP
4 0 PCIF1 Allow control of PCIF1 with assertion of SW PCI_STP
0 = Free Running, 1 = Stopped with SW PCI_STP
3 0 PCIF0 Allow control of PCIF0 with assertion of SW PCI_STP
0 = Free Running, 1 = Stopped with SW PCI_STP
2 1 PCIF2 PCIF2 Output Enable
0 = Disabled, 1 = Enabled
1 1 PCIF1 PCIF1 Output Enable
0 = Disabled, 1 = Enabled
0 1 PCIF0 PCIF0 Output Enable
0 = Disabled, 1 = Enabled
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CY28405OXC

Mfr. #:
Buy CY28405OXC
Manufacturer:
Cypress Semiconductor
Description:
IC CLOCK SYNTHESIZER 48SSOP
Lifecycle:
New from this manufacturer.
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