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CY28405OXC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
CY28405
Document #: 38-07512 Rev. *B Page 7 of 19
Byte 5: Control Register 5
Bit @Pup Name Description
7 1 DOT_48 DOT_48 Output Enable
0 = Disabled, 1 = Enabled
6 1 Reserved Reserved
5 HW 3V66_3/VCH/SELVCH 3V66_3/VCH/SELVCH Frequency Select
0 = 3V66 mode, 1 = VCH (48MHz) mode
May be written to override the power-up value.
4 1 3V66_3/VCH/SELVCH 3V66_3/VCH/SELVCH Output Enable
0 = Disabled,1 = Enabled
3 1 Reserved Reserved
2 1 3V66_2 3V66_2 Output Enable
0 = Disabled, 1 = Enabled
1 1 3V66_1 3V66_1 Output Enable
0 = Disabled, 1 = Enabled
0 1 3V66_0 3V66_0 Output Enable
0 = Disabled, 1 = Enabled
Byte 6: Control Register 6
Bit @Pup Name Description
70REF
PCIF
PCI
3V66
3V66_3/VCH/SELVCH
USB_48
DOT_48
CPUT, CPUT_ITP
CPUC,CPUC_ITP
Test Clock Mode
0 = Disabled, 1 = Enabled
When Test Clock Mode is enabled, the FS_A/REF_0 pin reverts to a
dedicated FS_A input, allowing asynchronous selection between Hi-Z and
REF/N mode.
6 0 Reserved Reserved, Set = 0
5 0 Reserved Reserved, Set = 0
4 0 Reserved Reserved, Set = 0
3 0 Reserved Reserved, Set = 0
20PCIF
PCI
3V66
CPUT,CPUT_ITP
CPUC,CPUC_ITP
Spread Spectrum Enable
0 = Spread Off, 1 = Spread On
1 1 REF_1 REF_1 Output Enable
0 = Disabled, 1 = Enabled
0 1 REF_0 REF_0 Output Enable
0 = Disabled, 1 = Enabled
Byte 7: Vendor ID
Bit @Pup Name Description
7 0 Revision Code Bit 3
6 1 Revision Code Bit 2
5 0 Revision Code Bit 1
4 0 Revision Code Bit 0
3 1 Vendor ID Bit 3
2 0 Vendor ID Bit 2
1 0 Vendor ID Bit 1
0 0 Vendor ID Bit 0
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CY28405
Document #: 38-07512 Rev. *B Page 8 of 19
Byte 8: Control Register 8
Bit @Pup Name Description
70CPU
PCIF
PCI
3V66
Spread Spectrum Selection
‘000’ = ±0.20% triangular
‘001’ = + 0.12, – 0.62%
‘010’ = + 0.25, – 0.75%
‘011’ = –0.05, – 0.45% triangular
‘100’ = ± 0.25%
‘101’ = + 0.00, – 0.50%
‘110’ = ± 0.5%
‘111’ = ± 0.38%
61
51
4 0 FSEL_4 SW Frequency selection bits. See Table 1.
3 0 FSEL_3
2 0 FSEL_2
1 0 FSEL_1
0 0 FSEL_0
Byte 9: Control Register 9
Bit @Pup Name Description
7 0 PCIF PCIF Clock Output Drive Strength Control
0 = Low Drive strength, 1 = High Drive strength
6 0 PCI PCI Clock Output Drive Strength
0 = Low Drive strength, 1 = High Drive strength
5 0 3V66 3V66 Clock Output Drive Strength
0 = Low Drive strength, 1 = High Drive strength
4 1 REF REF Clock Output Drive Strength
0 = Low Drive strength, 1 = High Drive strength
3 1 Reserved Reserved
2 1 Reserved Reserved
1 0 Reserved Vendor Test Mode (always program to 0)
0 0 Reserved Vendor Test Mode (always program to 0)
Byte 10: Control Register 10
Bit @Pup Name Description
7 0 PCI_Skew1 PCI skew control
00 = Normal
01 = –500 ps
10 = Reserved
11 = +500 ps
6 0 PCI_Skew0
5 0 3V66_Skew1 3V66 skew control
00 = Normal
01 = –150 ps
10 = +150 ps
11 = +300 ps
4 0 3V66_Skew0
3 1 Reserved Reserved, Set = 1
2 1 Reserved Reserved, Set = 1
1 1 Reserved Reserved, Set = 1
0 1 Reserved Reserved, Set = 1
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CY28405
Document #: 38-07512 Rev. *B Page 9 of 19
Byte 11: Control Register 11
Bit @Pup Name Description
7 0 Reserved Vendor Test Mode (always program to 0)
6 0 Recovery_Frequency This bit allows selection of the frequency setting that the clock will be
restored to once the system is rebooted
0: Use Hardware settings
1: Use Last SW table Programmed values
5 0 Watchdog Time Stamp
Reload
To enable this function the register bit must first be set to “0” before toggling
to “1”.
0: Do not reload
1: Reset timer but continue to count.
4 0 WD_Alarm This bit is set to “1” when the Watchdog times out. It is reset to “0” when
the system clears the WD_TIMER time stamp
3 0 WD_TIMER3 Watchdog timer time stamp selection:
0000: Off
0001: 2 second
0010: 4 seconds
0011: 6 seconds
.
.
.
1110: 28seconds
1111: 30seconds
2 0 WD_TIMER2
10WD_TIMER1
0 0 WD_TIMER0
Byte 12: Control Register 12
Bit @Pup Name Description
7 0 CPU_FSEL_N8 If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[8:0] and
CPU_FSEL_M[6:0] will be used to determine the CPU output frequency.
The setting of FS_Override bit determines the frequency ratio for CPU and
other output clocks. When it is cleared, the same frequency ratio stated in
the Latched FS[E:A] register will be used. When it is set, the frequency
ratio stated in the SEL[4:0] register will be used.
6 0 CPU_FSEL_N7
5 0 CPU_FSEL_N6
4 0 CPU_FSEL_N5
3 0 CPU_FSEL_N4
2 0 CPU_FSEL_N3
1 0 CPU_FSEL_N2
0 0 CPU_FSEL_N1
Byte 13: Control Register 13
Bit @Pup Name Description
7 0 CPU_FSEL_N0 If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[8:0] and
CPU_FSEL_M[6:0] will be used to determine the CPU output frequency.
The setting of FS_Override bit determines the frequency ratio for CPU and
other output clocks. When it is cleared, the same frequency ratio stated in
the Latched FS[E:A] register will be used. When it is set, the frequency
ratio stated in the SEL[4:0] register will be used.
60CPU_FSEL_M6
50CPU_FSEL_M5
40CPU_FSEL_M4
30CPU_FSEL_M3
20CPU_FSEL_M2
10CPU_FSEL_M1
00CPU_FSEL_M0
Byte 14: Control Register 14
Bit @Pup Name Description
7 0 FS_(E:A) FS_Override
0 = Select operating frequency by FS(E:A) input pins
1 = Select operating frequency by FSEL(4:0) settings
6 1 Reserved Reserved, Set = 1
5 0 Reserved Reserved, Set = 0
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P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

CY28405OXC

Mfr. #:
Buy CY28405OXC
Manufacturer:
Cypress Semiconductor
Description:
IC CLOCK SYNTHESIZER 48SSOP
Lifecycle:
New from this manufacturer.
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