AT91M55800-33AI Datasheet AT91M55800-33AI | P13-P15

AT91M55800A

1745CS–ATARM–05/02

Master Clock Master Clock is generated in one of the following ways, depending on programming in

the APMC registers:

• From the 32768 Hz low-power oscillator that clocks the RTC

• The on-chip main oscillator, together with a PLL, generate a software-programmable

main clock in the 500 Hz to 33 MHz range. The main oscillator can be bypassed to

allow the user to enter an external clock signal.

The Master Clock (MCK) is also provided as an output of the device on the MCKO pin,

whose state is controlled by the APMC module.

Reset Reset restores the default states of the user interface registers (defined in the user inter-

face of each peripheral), and forces the ARM7TDMI to perform the next instruction fetch

from address zero. Aside from the program counter, the ARM7TDMI registers do not

have defined reset states.

NRST Pin NRST is active low-level input. It is asserted asynchronously, but exit from reset is syn-

chronized internally to the MCK. At reset, the source of MCK is the Slow Clock (32768

Hz crystal), and the signal presented on MCK must be active within the specification for

a minimum of 10 clock cycles up to the rising edge of NRST, to ensure correct

operation.

Watchdog Reset The watchdog can be programmed to generate an internal reset. In this case, the reset

has the same effect as the NRST pin assertion, but the BMS and NTRI pins are not

sampled. Boot Mode and Tri-state Mode are not updated. If the NRST pin is asserted

and the watchdog triggers the internal reset, the NRST pin has priority.

Emulation Functions

Tri-state Mode The AT91M55800A provides a Tri-state Mode, which is used for debug purposes. This

enables the connection of an emulator probe to an application board without having to

desolder the device from the target board. In Tri-state Mode, all the output pin drivers of

the AT91M55800A microcontroller are disabled.

To enter Tri-state Mode, the NTRI pin must be held low during the last 10 clock cycles

before the rising edge of NRST. For normal operation the NTRI pin must be held high

during reset, by a resistor of up to 400K Ohm.

NTRI is multiplexed with I/O line PA18 and USART 1 serial data transmit line TXD1.

Standard RS232 drivers generally contain internal 400K Ohm pull-up resistors. If TXD1

is connected to a device not including this pull-up, the user must make sure that a high

level is tied on NTRI while NRST is asserted.

JTAG/ICE Debug Mode ARM Standard Embedded In-Circuit Emulation is supported via the JTAG/ICE port. It is

connected to a host computer via an external ICE Interface. The JTAG/ICE debug mode

is enabled when JTAGSEL is low.

In ICE Debug Mode the ARM Core responds with a non-JTAG chip ID which identifies

the core to the ICE system. This is not JTAG compliant.

AT91M55800A

1745CS–ATARM–05/02

IEEE 1149.1 JTAG Boundary-

scan

JTAG Boundary-scan is enabled when JTAGSEL is high. The functions SAMPLE,

EXTEST and BYPASS are implemented. There is no JTAG chip ID. The Special Func-

tion module provides a chip ID which is independent of JTAG.

It is not possible to switch directly between JTAG and ICE operations. A chip reset must

be performed (NRST and NTRST) after JTAGSEL is changed.

Memory Controller The ARM7TDMI processor address space is 4G bytes. The memory controller decodes

the internal 32-bit address bus and defines three address spaces:

• Internal memories in the four lowest megabytes

• Middle space reserved for the external devices (memory or peripherals) controlled

by the EBI

• Internal peripherals in the four highest megabytes

In any of these address spaces, the ARM7TDMI operates in Little-Endian mode only.

Internal Memories The AT91M55800A microcontroller integrates an 8-Kbyte primary SRAM bank. This

memory bank is mapped at address 0x0 (after the remap command), allowing

ARM7TDMI exception vectors between 0x0 and 0x20 to be modified by the software.

The rest of the bank can be used for stack allocation (to speed up context saving and

restoring), or as data and program storage for critical algorithms. All internal memory is

32 bits wide and single-clock cycle accessible. Byte (8-bit), half-word (16-bit) or word

(32-bit) accesses are supported and are executed within one cycle. Fetching Thumb or

ARM instructions is supported and internal memory can store twice as many Thumb

instructions as ARM ones.

Boot Mode Select The ARM reset vector is at address 0x0. After the NRST line is released, the

ARM7TDMI executes the instruction stored at this address. This means that this

address must be mapped in nonvolatile memory after the reset.

The input level on the BMS pin during the last 10 clock cycles before the rising edge of

the NRST selects the type of boot memory (see Table 5).

The BMS pin is multiplexed with the I/O line PB18 that can be programmed after reset

like any standard PIO line.

Remap Command The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction,

Interrupt, Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to

allow these vectors to be redefined dynamically by the software, the AT91M55800A

microcontroller uses a remap command that enables switching between the boot mem-

ory and the internal RAM bank addresses. The remap command is accessible through

the EBI User Interface, by writing one in RCB of EBI_RCR (Remap Control Register).

Performing a remap command is mandatory if access to the other external devices (con-

nected to chip selects 1 to 7) is required. The remap operation can only be changed

back by an internal reset or an NRST assertion.

Table 6. Boot Mode Select

BMS Boot Mode

1 External 8-bit memory on NCS0

0 External 16-bit memory on NCS0

AT91M55800A

1745CS–ATARM–05/02

Abort Control The abort signal providing a Data Abort or a Prefetch Abort exception to the ARM7TDMI

is asserted when accessing an undefined address in the EBI address space.

No abort is generated when reading the internal memory or by accessing the internal

peripherals, whether the address is defined or not.

External Bus Interface The External Bus Interface handles the accesses between addresses 0x0040 0000 and

0xFFC0 0000. It generates the signals that control access to the external devices, and

can configure up to eight 16-Mbyte banks. In all cases it supports byte, half-word and

word aligned accesses.

For each of these banks, the user can program:

• Number of wait states

• Number of data float times (wait time after the access is finished to prevent any bus

contention in case the device is too long in releasing the bus)

• Data bus width (8-bit or 16-bit)

• With a 16-bit wide data bus, the user can program the EBI to control one 16-bit

device (Byte Access Select Mode) or two 8-bit devices in parallel that emulate a 16-

bit memory (Byte-write Access mode).

The External Bus Interface features also the Early Read Protocol, configurable for all the

devices, that significantly reduces access time requirements on an external device.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

AT91M55800-33AI

Mfr. #:

Buy AT91M55800-33AI

Manufacturer:

Description:

IC MCU 16/32BIT ROMLESS 176TQFP

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet

AT91M55800-33AI