17
AT91M55800A
1745CS–ATARM–05/02
System Peripherals
APMC: Advanced Power
Management Controller
The AT91M55800A Advanced Power Management Controller allows optimization of
power consumption. The APMC enables/disables the clock inputs of most of the periph-
erals and the ARM core. Moreover, the main oscillator, the PLL and the analog
peripherals can be put in standby mode allowing minimum power consumption to be
obtained. The APMC provides the following operating modes:
• Normal mode: clock generator provides clock to the entire chip except the RTC.
• Wait mode: ARM core clock deactivated
• Slow Clock mode: clock generator deactivated, master clock 32 kHz
• Standby mode: RTC active, all other clocks disabled
• Power-down mode: RTC active, supply on the rest of the circuit deactivated
RTC: Real Time Clock The AT91M55800A features a Real-time Clock (RTC) peripheral that is designed for
very low power consumption. It combines a complete time-of-day clock with alarm and a
two-hundred year Gregorian calendar, complemented by a programmable periodic
interrupt.
The time and calendar values are coded in Binary-Coded Decimal (BCD) format. The
time format can be 24-hour mode or 12-hour mode with an AM/PM indicator.
Updating time and calendar fields and configuring the alarm fields is performed by a par-
allel capture on the 32-bit data bus. An entry control is performed to avoid loading
registers with incompatible BCD format data or with an incompatible date according to
the current month/ year/century.
AIC: Advanced Interrupt
Controller
The AIC has an 8-level priority, individually maskable, vectored interrupt controller, and
drives the NIRQ and NFIQ pins of the ARM7TDMI from:
• The external fast interrupt line (FIQ)
• The six external interrupt request lines (IRQ0 - IRQ5)
• The interrupt signals from the on-chip peripherals
The AIC is largely programmable offering maximum flexibility, and its vectoring features
reduce the real-time overhead in handling interrupts.
The AIC also features a spurious vector, which reduces spurious interrupt handling to a
minimum, and a protect mode that facilitates the debug capabilities.
PIO: Parallel I/O Controller The AT91M55800A has 58 programmable I/O lines. 13 pins are dedicated as general-
purpose I/O pins. The other I/O lines are multiplexed with an external signal of a periph-
eral to optimize the use of available package pins. The PIO lines are controlled by two
separate and identical PIO Controllers called PIOA and PIOB. The PIO controller
enables the generation of an interrupt on input change and insertion of a simple input
glitch filter on any of the PIO pins.
WD: Watchdog The Watchdog is built around a 16-bit counter, and is used to prevent system lock-up if
the software becomes trapped in a deadlock. It can generate an internal reset or inter-
rupt, or assert an active level on the dedicated pin NWDOVF. All programming registers
are password-protected to prevent unintentional programming.
SF: Special Function The AT91M55800A provides registers which implement the following special functions.
• Chip identification
• RESET status
