4
AT91M55800A
1745CS–ATARM–05/02
J1 A17 L1 A20 N1 D4 R1 D10
J2 A18 L2 A23 N2 D6 R2 D11
J3 VDDIO L3 D0 N3 VDDIO R3 D12
J4 A16 L4 D1 N4 D14 R4 D13
J5 L5 N5 PB19/TCLK0 R5 PB20/TIOA0
J6 L6 N6 VDDIO R6 PB23/TIOA1
J7 L7 N7 PB25/TCLK2 R7 PB24/TIOB1
J8 L8 N8 PA1/TIOA3 R8 PA3/TCLK4
J9 L9 N9 VDDIO R9 PA4/TIOA4
J10 L10 N10 PA8/TIOB5 R10 PA5/TIOB4
J11 L11 N11 PA9/IRQ0 R11 PA6/TCLK5
J12 PA29/NPCS3 L12 PA25/MOSI N12 VDDCORE R12 PA12/IRQ3
J13 SHDN L13 PA22RXD2 N13 VDDIO R13 PA14/SCK0
J14 VDDPLL L14 PA26/NPCS0/NSS N14 PA19/RXD1 R14 PA15/TXD0
J15 PLLRC L15 XOUT N15 GND R15 PA16/RXD0
K1 A19 M1 D2 P1 D5
K2 A22 M2 D3 P2 D7
K3 A21 M3 VDDCORE P3 D8
K4 GND M4 GND P4 D9
K5 M5 GND P5 D15
K6 M6 PB21/TIOB0 P6 PB22/TCLK1
K7 M7 GND P7 PB26/TIOA2
K8 M8 PB27/TIOB2 P8 PA2/TIOB3
K9 M9 PA0/TCLK3 P9 PA7/TIOA5
K10 M10 GND P10 PA10/IRQ1
K11 M11 PA23/SPCK P11 PA11/IRQ2
K12 PA28/NPCS2 M12 GND P12 PA13/FIQ
K13 VDDIO M13 PA21/TXD2 P13 PA17SCK1
K14 PA27/NPCS1 M14 PA24/MISO P14 PA18/TXD1/NTRI
K15 GNDPLL M15 XIN P15 PA20/SCK2
Table 2. Pin Configuration for 176-ball BGA Package (Continued)
Pin AT91M55800A Pin AT91M55800A Pin AT91M55800A Pin AT91M55800A
5
AT91M55800A
1745CS–ATARM–05/02
Figure 1. 176-lead TQFP Pinout
Figure 2. 176-ball BGA Pinout
144
176
133
132 89
45
88
123456789101112
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
13 14 15
6
AT91M55800A
1745CS–ATARM–05/02
Pin Description
Table 3. Pin Description
Module Name Function Type
Active
Level Comments
EBI
A0 - A23 Address bus Output
D0 - D15 Data bus I/O
NCS0 - NCS7 Chip select Output Low
NWR0 Lower byte 0 write signal Output Low Used in Byte-write option
NWR1 Lower byte 1 write signal Output Low Used in Byte-write option
NRD Read signal Output Low Used in Byte-write option
NWE Write enable Output Low Used in Byte-select option
NOE Output enable Output Low Used in Byte-select option
NUB Upper byte-select Output Low Used in Byte-select option
NLB Lower byte-select Output Low Used in Byte-select option
NWAIT Wait input Input Low
BMS Boot mode select Input Sampled during reset
AIC
IRQ0 - IRQ5 External interrupt request Input PIO-controlled after reset
FIQ Fast external interrupt request Input PIO-controlled after reset
Timer
TCLK0 - TCLK5 Timer external clock Input PIO-controlled after reset
TIOA0 - TIOA5 Multipurpose timer I/O pin A I/O PIO-controlled after reset
TIOB0 - TIOB5 Multipurpose timer I/O pin B I/O PIO-controlled after reset
USART
SCK0 - SCK2 External serial clock I/O PIO-controlled after reset
TXD0 - TXD2 Transmit data output Output PIO-controlled after reset
RXD0 - RXD2 Receive data input Input PIO-controlled after reset
SPI
SPCK SPI clock I/O PIO-controlled after reset
MISO Master in slave out I/O PIO-controlled after reset
MOSI Master out slave in I/O PIO-controlled after reset
NSS Slave select Input Low PIO-controlled after reset
NPCS0 - NPCS3 Peripheral chip select Output Low PIO-controlled after reset
PIO
PA0 - PA29 Parallel I/O port A I/O Input after reset
PB0 - PB27 Parallel I/O port B I/O Input after reset
WD NWDOVF Watchdog timer overflow Output Low Open drain
ADC
AD0 - AD7 Analog input channels 0 - 7 Analog in
AD0TRIG ADC0 external trigger Input PIO-controlled after reset
AD1TRIG ADC1 external trigger Input PIO-controlled after reset
ADVREF Analog reference Analog ref
DAC
DA0 - DA1 Analog output channels 0 - 1 Analog out
DAVREF Analog reference Analog ref

AT91M55800-33AI

Mfr. #:
Manufacturer:
Description:
IC MCU 16/32BIT ROMLESS 176TQFP
Lifecycle:
New from this manufacturer.
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