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CY14V256LA-BA35XIT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
CY14V256LA
256-Kbit (32 K × 8) nvSRAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-76295 Rev. *D Revised March 20, 2015
256-Kbit (32 K × 8) nvSRAM
Features
■ 35 ns access time
■ Internally organized as 32 K × 8
■ Hands off automatic STORE on power down with only a small
capacitor
■ STORE to QuantumTrap nonvolatile elements initiated by
software, device pin, or AutoStore on power down
■ RECALL to SRAM initiated by software or power up
■ Infinite read, write, and recall cycles
■ 1 million STORE cycles to QuantumTrap
■ 20 year data retention
■ Core V
CC
= 3.0 V to 3.6 V; I/O V
CCQ
= 1.65 V to 1.95 V
■ Industrial temperature
■ 48-ball fine-pitch ball grid array (FBGA) package
■ Pb-free and restriction of hazardous substances (RoHS)
compliance
Functional Description
The Cypress CY14V256LA is a fast static RAM, with a
nonvolatile element in each memory cell. The memory is
organized as 32 K bytes of 8 bits each. The embedded
nonvolatile elements incorporate QuantumTrap technology,
producing the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, while independent
nonvolatile data resides in the highly reliable QuantumTrap cell.
Data transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power-up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.
For a complete list of related documentation, click here.
STORE/
RECALL
CONTROL
POWER
CONTROL
SOFTWARE
DETECT
STATIC RAM
ARRAY
512 X 512
Quantum Trap
512 X 512
STORE
RECALL
COLUMN I/O
COLUMN DEC
ROW DECODER
INPUT BUFFERS
OE
CE
WE
HSB
V
CC
V
CAP
A
14
-
A
2
A
0
A
1
A
2
A
3
A
4
A
10
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
Logic Block Diagram
V
CCQ
Logic Block Diagram
CY14V256LA
Document Number: 001-76295 Rev. *D Page 2 of 22
Contents
Pinout ................................................................................ 3
Pin Definitions .................................................................. 3
Device Operation.............................................................. 4
SRAM Read ................................................................ 4
SRAM Write................................................................. 4
AutoStore Operation.................................................... 4
Hardware STORE Operation....................................... 4
Hardware RECALL (Power-Up) .................................. 5
Software STORE......................................................... 5
Software RECALL ....................................................... 5
Preventing AutoStore .................................................. 6
Data Protection............................................................ 6
Maximum Ratings............................................................. 7
Operating Range............................................................... 7
DC Electrical Characteristics .......................................... 7
Data Retention and Endurance ....................................... 8
Capacitance ...................................................................... 8
Thermal Resistance.......................................................... 8
AC Test Loads .................................................................. 9
AC Test Conditions.......................................................... 9
AC Switching Characteristics ....................................... 10
SRAM Read Cycle .................................................... 10
SRAM Write Cycle..................................................... 10
Switching Waveforms.................................................... 11
AutoStore/Power-up RECALL....................................... 13
Switching Waveforms.................................................... 14
Software Controlled STORE/RECALL Cycle................ 15
Switching Waveforms.................................................... 15
Hardware STORE Cycle................................................. 16
Switching Waveforms.................................................... 16
Truth Table For SRAM Operations................................ 17
Ordering Information...................................................... 18
Ordering Code Definitions......................................... 18
Package Diagrams.......................................................... 19
Acronyms........................................................................ 20
Document Conventions................................................. 20
Units of Measure....................................................... 20
Document History Page................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support....................... 22
Products.................................................................... 22
PSoC Solutions......................................................... 22
CY14V256LA
Document Number: 001-76295 Rev. *D Page 3 of 22
Pinout
Figure 1. 48-ball FBGA (6 × 10 × 1.2 mm) pinout
WE
V
CCQ
A
11
A
10
V
CAP
A
6
A
0
A
3
CE
NC
DQ
0
A
4
A
5
NC
DQ
2
DQ
3
NC
V
SS
A
9
A
8
OE
V
SS
A
7
NC
NC
V
CC
NC
A
2
A
1
NC
V
CCQ
DQ
4
NC
DQ
5
DQ
6
NC DQ
7
NC
A
14
A
13
A
12
HSB
3
2
6
5
4
1
D
E
B
A
C
F
G
H
NC
NC
DQ
1
(not to scale)
Top View
(× 8)
V
SS
V
SS
V
CC
Pin Definitions
Pin Name I/O Type Description
A
0
–A
14
Input Address inputs. Used to select one of the 32,768 bytes of the nvSRAM.
DQ
0
–DQ
7
Input/Output Bidirectional data I/O lines. Used as input or output lines depending on operation.
WE
Input Write enable input, active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
CE
Input Chip enable input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input Output enable, active LOW. The active LOW OE input enables the data output buffers during read cycles.
I/O pins are tri-stated on deasserting OE
HIGH.
V
SS
Ground Ground for the device. Must be connected to the ground of the system.
V
CC
Power supply Power supply inputs to the core of the device.
V
CCQ
Power supply Power supply inputs for the inputs and outputs of the device.
HSB
Input/Output Hardware STORE busy (HSB). When LOW, this output indicates that a Hardware STORE is in progress.
When pulled LOW, external to the chip, it initiates a nonvolatile STORE operation. After each hardware
and software STORE operation HSB
is driven HIGH for a short time (t
HHHD
) with standard output high
current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection
optional).
V
CAP
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
NC No connect No connect. This pin is not connected to the die.
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CY14V256LA-BA35XIT

Mfr. #:
Buy CY14V256LA-BA35XIT
Manufacturer:
Cypress Semiconductor
Description:
NVRAM 256Kb 35ns 32K x 8 nvSRAM
Lifecycle:
New from this manufacturer.
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