Document Number: 001-76295 Rev. *D Page 10 of 22
AC Switching Characteristics
Over the Operating Range
Parameters
[9]
Description
35 ns
Unit
Cypress
Parameters
Alt
Parameters
Min Max
SRAM Read Cycle
t
ACE
t
ACS
Chip enable access time – 35 ns
t
RC
[10]
t
RC
Read cycle time 35 – ns
t
AA
[11]
t
AA
Address access time – 35 ns
t
DOE
t
OE
Output enable to data valid – 15 ns
t
OHA
[11]
t
OH
Output hold after address change 3 – ns
t
LZCE
[12, 13]
t
LZ
Chip enable to output active 3 – ns
t
HZCE
[12, 13]
t
HZ
Chip disable to output inactive – 13 ns
t
LZOE
[12, 13]
t
OLZ
Output enable to output active 0 – ns
t
HZOE
[12, 13]
t
OHZ
Output disable to output inactive – 13 ns
t
PU
[12]
t
PA
Chip enable to power active 0 – ns
t
PD
[12]
t
PS
Chip disable to power standby – 35 ns
SRAM Write Cycle
t
WC
t
WC
Write cycle time 35 – ns
t
PWE
t
WP
Write pulse width 25 – ns
t
SCE
t
CW
Chip enable to end of write 25 – ns
t
SD
t
DW
Data setup to end of write 12 – ns
t
HD
t
DH
Data hold after end of write 0 – ns
t
AW
t
AW
Address setup to end of write 25 – ns
t
SA
t
AS
Address setup to start of write 0 – ns
t
HA
t
WR
Address hold after end of write 0 – ns
t
HZWE
[12, 13, 14]
t
WZ
Write enable to output disable – 13 ns
t
LZWE
[12, 13]
t
OW
Output active after end of write 3 – ns
Notes
9. Test conditions assume signal transition time of 1.8 ns or less, timing reference levels of V
CCQ
/2, input pulse levels of 0 to V
CC Q(typ)
, and output loading of the specified
I
OL
/I
OH
and load capacitance shown in Figure 3 on page 9.
10. WE
must be HIGH during SRAM read cycles.
11. Device is continuously selected with CE
and OE LOW.
12. These parameters are guaranteed by design and are not tested.
13. Measured ±200 mV from steady state output voltage.
14. If WE
is low when CE goes low, the outputs remain in the high-impedance state.
