952601EGLF Datasheet 952601EGLFT, 952601EFLF, 952601EGLF | P13-P15

IDT

Progammable Timing Control Hub

for Next Gen P4

Processor 701J—01/25/10

ICS952601

Programmable Timing Control Hub

for Next Gen P4

Processor

C Table: Output Control and Fix Frequency Register

Pin # Name Control Function T

e0 1 PWD

Bit 7 Test Clock Mode Test Clock Mode - Disable Enable 0

Bit 6

RESERVED - - - - 0

Bit 5

RESERVED

FS_A and FS_B

eration

- Normal Test Mode 0

Bit 4

RESERVED

SRC Frequency

Select

- 100MHz 200MHz 0

Bit 3

RESERVED - - - - 0

Bit 2 Spread Spectrum Mode Spread OFF

Spread

Bit 1 REF1 Out

ut Control RW Disable Enable 1

Bit 0 REF0 Output Control RW Disable Enable 1

C Table: Vendor & Revision ID Register

Pin # Name Control Function T

pe 0 1 PWD

Bit 7 RID3 R - - X

Bit 6 RID2 R - - X

Bit 5

RID1 R - - X

Bit 4

RID0 R - - X

Bit 3

VID3 R - - 0

Bit 2 VID2 R - - 0

Bit 1 VID1 R - - 0

Bit 0 VID0 R - - 1

1,2,7,8,9,12,13,14,1

5,18,19,20,22,23,26,

27,29,31,32,37,38,4

0,41,43,44,46,47

40,41,43,44,46,47

Byte 6

37,38

7,8,9,12,13,14,15,18

,19,20,22,23,26,27,2

9,31,32,37,38,40,41,

43,44,46,47

Byte 7

REVISION ID

VENDOR ID

IDT

Progammable Timing Control Hub

for Next Gen P4

Processor 701J—01/25/10

ICS952601

Programmable Timing Control Hub

for Next Gen P4

Processor

The PCI_STOP# signal is on an active low input controlling PCI and SRC outputs. If PCIF (2:0) and SRC clocks can be set to

be free-running through I2C programming. Outputs set to be free-running will ignore both the PCI_STOP pin and the

PCI_STOP register bit.

PCI Stop Functionality

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The clock samples the PCI_STOP# signal on a rising edge of PCIF clock. After detecting the PCI_STOP# assertion low, all

PCI[6:0] and stoppable PCIF[2:0] clocks will latch low on their next high to low transition. After the PCI clocks are latched low,

the SRC clock, (if set to stoppable) will latch high at Iref * 6 (or tristate if Byte 2 Bit 6 = 1) upon its next low to high transition and

the SRC# will latch low as shown below.

PCI_STOP#

Tsu

PCIF[2:0] 33MHz

PCI[6:0] 33MHz

SRC 100MHz

SRC# 100MHz

PCI_STOP# Assertion (transition from '1' to '0')

The de-assertion of the PCI_Stop# signal is to be sampled on the rising edge of the PCIF free running clock domain. After

detecting PCI_Stop# de-assertion, all PCI[6:0], stoppable PCIF[2:0] and stoppable SRC clocks will resume in a glitch free

manner.

PCI_STOP#

Tsu

Tdrive_SRC

PCIF[2:0] 33MHz

PCI[6:0] 33MHz

SRC 100MHz

SRC# 100MHz

PCI_STOP# - De-assertion

IDT

Progammable Timing Control Hub

for Next Gen P4

Processor 701J—01/25/10

ICS952601

Programmable Timing Control Hub

for Next Gen P4

Processor

The CPU_STOP# signal is an active low input controlling the CPU outputs. This signal can be asserted asynchronously.

CPU_STOP# Functionality

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Asserting CPU_STOP# pin stops all CPU outputs that are set to be stoppable after their next transition. When the I2C

CPU_STOP tri-state bit corresponding to the CPU output of interest is programmed to a '0', CPU output will stop CPU_True

= HIGH and CPU_Complement = LOW. When the I2C CPU_Stop tri-state bit corresponding to the CPU output of interest is

programmed to a '1', CPU outputs will be tri-stated.

CPU_STOP#

CPU

CPU#

CPU_STOP# - Assertion (transition from '1' to '0')

With the de-assertion of CPU_Stop# all stopped CPU outputs will resume without a glitch. The maximum latency from the

de-assertion to active outputs is 2 - 6 CPU clock periods. If the control register tristate bit corresponding to the output of

interest is programmed to '1', then the stopped CPU outputs will be driven High within 10nS of CPU_Stop# de-assertion to

a voltage greater than 200mV.

CPU_Stop#

Tdrive_CPU_Stop, 10nS >200mV

CPU

CPU#

CPU Internal

CPU_STOP# - De-assertion (transition from '0' to '1')

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

952601EGLF

Mfr. #:

Buy 952601EGLF

Manufacturer:

IDT

Description:

Clock Generators & Support Products PC MAIN CLOCK

Lifecycle:

New from this manufacturer.

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952601EGLF

952601EGLF

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