952601EGLF Datasheet 952601EGLFT, 952601EFLF, 952601EGLF | P19-P21

IDT

Progammable Timing Control Hub

for Next Gen P4

Processor 701J—01/25/10

ICS952601

Programmable Timing Control Hub

for Next Gen P4

Processor

The following diagrams illustrate CPU clock timing during CPU_Stop# and PwrDwn# modes with CPU_PwrDwn and

CPU_Stop tristate control bits set to driven or tristate in byte 2 of the control register.

CPU_Stop = Driven, CPU_Pwrdwn = Driven

CPU_Stop#

1.8mS

PD#

CPU (Free Running)

CPU# (Free Running)

CPU (Stoppable)

CPU# (Stoppable)

Notes:

1. When both bits (CPU_Stop & CPU_Pwrdown tristate bits) are low, the clock chip will never tristate CPU output clocks

(assuming clock's OE bit is set to "1")

CPU Clock Tristate Timing

CPU_Stop = Tristate, CPU_Pwrdwn = Driven

CPU_Stop#

1.8mS

PD#

CPU (Free Running)

CPU# (Free Running)

CPU (Stoppable)

CPU# (Stoppable)

Notes:

1. Tristate outputs are pulled low by output termination resistors as shown here.

IDT

Progammable Timing Control Hub

for Next Gen P4

Processor 701J—01/25/10

ICS952601

Programmable Timing Control Hub

for Next Gen P4

Processor

CPU_Stop = Driven, CPU_Pwrdwn = Tristate

CPU_Stop#

1.8mS

PWRDWN#

CPU (Free Running)

CPU# (Free Running)

CPU (Stoppable)

CPU# (Stoppable)

Notes:

1. When CPU_Pwrdwn is set to tristate and CPU_Stop is set to driven, the clock chip will tristate outputs only during the

assertion of PWRDWN#. Differential clock behavior during the assertion/de-assertion of CPU_Stop# will be unaffected.

2. In the case that CPU_Stop# is de-asserted during the 1.8mS PWRDWN# de-assertion resume delay, the clock chip can

sample the CPU_Stop# high with the internal rising edges of clock#. This will result in CPU clocks resuming immediately

after the 1.8mS windows expires. This applies to all control register bit changes as well.

3. Tristate outputs are pulled low by output termination resistors as shown here.

CPU_Stop = Tristate, CPU_Pwrdwn = Tristate

CPU_Stop#

1.8mS

PWRDWN#

CPU (Free Running)

CPU# (Free Running)

CPU (Stoppable)

CPU# (Stoppable)

Notes:

1. When CPU_Stop and CPU_Pwrdwn bits are set to tristate, the clock chip will tristate the outputs during the assertion of

CPU_Stop# and PWRDWN#.

2. Tristate outputs are pulled low by output termination resistors as shown here.

IDT

Progammable Timing Control Hub

for Next Gen P4

Processor 701J—01/25/10

ICS952601

Programmable Timing Control Hub

for Next Gen P4

Processor

The following diagrams illustrate SRC clock timing during PCI_Stop# and PwrDwn# modes with SRC_Pwrdwn and

SRC_Stop tristate control bits set to driven or tristate in byte 2 of the control register.

SRC_Stop = Driven, SRC_Pwrdwn = Driven

PCI_Stop#

1.8mS

PWRDWN#

PCI (Free Running)

CPU (Free Running)

CPU# (Free Running)

SRC (Stoppable)

SRC# (Stoppable)

1 PCI

clock max

Notes:

1. When both bits (SRC_Stop & SRC_Pwrdown tristate bits) are set to driven, the clock chip will never tristate the SRC output

clock (assuming clock's OE bit is set to "1")

SRC Clock Tristate Timing

SRC_Stop = Tristate, Pwrdwn = Tristate

PCI_Stop#

1.8mS

PWRDWN#

PCI (Free Running)

CPU (Free Running)

CPU# (Free Running)

SRC (Stoppable)

SRC# (Stoppable)

1 PCI

clock max

Notes:

1. When SRC_Stop and SRC_Pwrdwn bits are set to tristate, the clock chip will tristate outputs during the assertion of

PCI_Stop# and PWRDWN#.

2. Tristate outputs are pulled low by output termination resistors as shown here.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

952601EGLF

Mfr. #:

Buy 952601EGLF

Manufacturer:

IDT

Description:

Clock Generators & Support Products PC MAIN CLOCK

Lifecycle:

New from this manufacturer.

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952601EGLF

952601EGLF

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