952601EGLF Datasheet 952601EGLFT, 952601EFLF, 952601EGLF | P4-P6

IDT

Progammable Timing Control Hub

for Next Gen P4

Processor 701J—01/25/10

ICS952601

Programmable Timing Control Hub

for Next Gen P4

Processor

General Description

Block Diagram

Power Groups

ICS952601 follows Intel CK409 Yellow Cover specification. This clock synthesizer provides a single chip solution for next

generation P4 Intel processors and Intel chipsets. ICS952601 is driven with a 14.318MHz crystal. It generates CPU outputs up

to 200MHz. It also provides a tight ppm accuracy output for Serial ATA support.

I REF

PLL2

Frequency

Dividers

Programmable

Spread

PLL1

Programmable

Frequency

Dividers

STOP

Logic

48MHz, USB, DOT, VCH

XTAL

SDATA

SCLK

CPU_STOP#

PCI_STOP#

Vtt_PWRGD#

PD#

FS_A

FS_B

Control

Logic

REF (1:0)

CPUCLKT (2:0)

CPUCLKC (2:0)

SRCCLKT0

SRCCLKC0

3V66(4:0)

PCICLK (6:0)

PCICLKF (2:0)

VDD GND

3 6 Xtal, Ref

24 25 3V66 [0:3]

10,16 11,17 PCICLK outputs

36 39 SRCCLK outputs

55 54 Master clock, CPU Analog

34 33 48MHz, PLL, SCLK, SDATA

N/A 53 IREF

48, 42 45 CPUCLK clocks

Description

Pin Number

IDT

Progammable Timing Control Hub

for Next Gen P4

Processor 701J—01/25/10

ICS952601

Programmable Timing Control Hub

for Next Gen P4

Processor

Absolute Maximum Ratings

Symbol Parameter Min Max Units Notes

VDD_A 3.3V Core Supply Voltage VDD + 0.5V V

VDD_In 3.3V Logic Input Supply Voltage GND - 0.5 VDD + 0.5V V

Ts Storage Temperature -65 150 °C

Tambient Ambient Operating Temp 0 70 °C

Tcase1 Case Temperature 1 115 °C 1

Tcase2 Case Temperature 2 94 °C 2

ESD prot Input ESD protection human body model 2000 V

1. This case temperature limits the junction temperature to <150 °C for package reliabilty

2. This case temperature limits the junction temperature to <125 °C for long term silicon reliability

Electrical Characteristics - Input/Supply/Common Output Parameters

= 0 - 70°C; Supply Voltage V

= 3.3 V +/-5%

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

Input High Voltage V

3.3 V +/-5% 2 V

+ 0.3 V

Input MID Voltage V

MID

3.3 V +/-5% 1 1.8 V

Input Low Voltage V

3.3 V +/-5% V

- 0.3 0.8 V

Input High Current I

= V

-5 5 uA

IL1

= 0 V; Inputs with no pull-

up resistors

-5 uA

IL2

= 0 V; Inputs with pull-up

resistors

-200 uA

Operating Supply Current I

DD3. 3OP

Full Active, C

= Full load;

258

350 mA

all diff pairs driven 29 35 mA

all differential pairs tri-stated 0.3 12 mA

Input Frequency

= 3.3 V 14.31818 MHz 3

Pin Inductance

7nH1

Logic Inputs 5 pF 1

OUT

Output pin capacitance 6 pF 1

INX

X1 & X2 pins 5 pF 1

Clk Stabilization

1,2

STAB

From V

Power-Up or de-

assertion of PD# to 1st clock

1.8 ms 1,2

Modulation Frequency Triangular Modulation 30 33 kHz 1

Tdrive_SRC

SRC output enable after

PCI_Stop# de-assertion

15 ns 1

Tdrive_PD#

CPU output enable after

PD# de-assertion

300 us 1

Tfall_Pd# PD# fall time of 5 ns 1

Trise_Pd# PD# rise time of 5 ns 2

Tdrive_CPU_Stop#

CPU output enable after

CPU_Stop# de-assertion

10 us 1

Tfall_CPU_Stop# PD# fall time of 5 ns 1

Trise_CPU_Stop# PD# rise time of 5 ns 2

SMBus Voltage V

2.7 5.5 V 1

Low-level Output Voltage V

@ I

PULLUP

0.4 V 1

Current sinking at V

= 0.4 V I

PULLUP

4mA1

SCLK/SDATA

Clock/Data Rise Time

RI2C

(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1

SCLK/SDATA

Clock/Data Fall Time

FI2C

(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1

Guaranteed b

desi

n, not 100% tested in production.

See timing diagrams for timing requirements.

DD3. 3PD

Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency

accuracy on PLL outputs.

Input Capacitance

Input Low Current

Powerdown Current

IDT

Progammable Timing Control Hub

for Next Gen P4

Processor 701J—01/25/10

ICS952601

Programmable Timing Control Hub

for Next Gen P4

Processor

Electrical Characteristics - CPU & SRC 0.7V Current Mode Differential Pair

= 0 - 70°C; V

= 3.3 V +/-5%; C

=2pF

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

Current Source Output

Impedance

= V

3000

Ω

Voltage High VHigh 660 770 850 1

Voltage Low VLow -150 5 150 1

Max Volta

e Vovs 756 1150 1

Min Volta

e Vuds -300 -7 1

Crossin

Volta

e (abs) Vcross(abs) 250 350 550 mV 1

Crossing Voltage (var) d-Vcross

Variation of crossing over all

12 140 mV 1

Lon

Accuracy ppm see Tperiod min-max values -300 300 ppm 1,2

200MHz nominal 4.9985 5.0000 5.0015 ns 2

200MHz spread 4.9985 5.0266 ns 2

166.66MHz nominal 5.9982 6.0000 6.0018 ns 2

166.66MHz spread 5.9982 6.0320 ns 2

133.33MHz nominal 7.4978 7.5000 7.5023 ns 2

133.33MHz spread 7.4978 5.4000 ns 2

100.00MHz nominal 9.9970 10.0000 10.0030 ns 2

100.00MHz spread 9.9970 10.0533 ns 2

200MHz nominal 4.8735 ns 1,2

166.66MHz nominal/spread 5.8732 ns 1,2

133.33MHz nominal/spread 7.3728 ns 1,2

100.00MHz nominal/spread 9.8720 ns 1,2

Rise Time t

= 0.175V, V

= 0.525V 175 332 700 ps 1

Fall Time t

= 0.525V V

= 0.175V 175 344 700 ps 1

Rise Time Variation d-t

30 125 ps 1

Fall Time Variation d-t

30 125 ps 1

Duty Cycle d

Measurement from differential

wavefrom

45 49 55 % 1

Skew t

sk3

= 50% 8 100 ps 1

Jitter, Cycle to cycle t

jcyc-cyc

Measurement from differential

wavefrom

37 125 ps 1

Guaranteed by desi

n, not 100% tested in production.

SRC clock outputs run at only 100MHz or 200MHz, specs for 133.33 and 166.66 do not apply to SRC clock pair.

All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at

14.31818MHz

TperiodAverage period

Absolute min period T

absmin

Statistical measurement on

single ended signal using

oscilloscope math function.

Measurement on single ended

nal usin

absolute value.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

952601EGLF

Mfr. #:

Buy 952601EGLF

Manufacturer:

IDT

Description:

Clock Generators & Support Products PC MAIN CLOCK

Lifecycle:

New from this manufacturer.

Delivery:

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952601EGLF

952601EGLF

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