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952601EGLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
IDT
TM
Progammable Timing Control Hub
TM
for Next Gen P4
TM
Processor 701J—01/25/10
ICS952601
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor
22
PCI_STOP Asserted
SRC_Stop = Tristate, SRC_Pwrdwn = Tristate
PCI_Stop#
1.8mS
PWRDWN#
PCI (Free Running)
CPU (Free Running)
CPU# (Free Running)
SRC (Stoppable)
SRC# (Stoppable)
Notes:
1. When SRC_Pwrdwn and SRC_Stop are set to tristate, the clock chip will tristate outputs during the assertion of PCI_Stop#
and PWRDWN#.
2. In the case that PCI_Stop# is de-asserted during the 1.8mS PWRDWN# de-assertion resume delay, the clock chip can
sample the PCI_Stop# high with the internal rising edges of CPU clock#. This will result in SRC clocks resuming
immediately after the 1.8mS window expires. This applies to all control register bit changes as well.
3. Tristate outputs are pulled low by output termination resistors as shown here.
IDT
TM
Progammable Timing Control Hub
TM
for Next Gen P4
TM
Processor 701J—01/25/10
ICS952601
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor
23
MIN MAX MIN MAX
A 2.41 2.80 .095 .110
A1 0.20 0.40 .008 .016
b 0.20 0.34 .008 .0135
c 0.13 0.25 .005 .010
D
E 10.03 10.68 .395 .420
E1 7.40 7.60 .291 .299
e
h 0.38 0.64 .015 .025
L 0.50 1.02 .020 .040
N
a0°8°0°8°
VARIATIONS
MIN MAX MIN MAX
56 18.31 18.55 .720 .730
10-0034
0.635 BASIC 0.025 BASIC
COMMON DIMENSIONS
In Millimeters In Inches
COMMON DIMENSIONS
Reference Doc.: JEDEC Publication 95, MO-118
56-Lead, 300 mil Body, 25 mil, SSOP
N
SEE VARIATIONS SEE VARIATIONS
D mm. D (inch)
SYMBOL
SEE VARIATIONS SEE VARIATIONS
INDEX
AREA
INDEX
AREA
1 2
N
D
h x 45°
E1
E
α
SEATING
PLANE
SEATING
PLANE
A1
A
e
- C -
b
.10 (.004) C
.10 (.004) C
c
L
Ordering Information
952601yFLFT
Example:
Designation for tape and reel packaging
Annealed Lead Free (optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
XXXX y F LF T
IDT
TM
Progammable Timing Control Hub
TM
for Next Gen P4
TM
Processor 701J—01/25/10
ICS952601
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor
24
INDEX
AREA
INDEX
AREA
12
1 2
N
D
E1
E
a
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
-C-
- C -
b
c
L
aaa
C
MIN MAX MIN MAX
A -- 1.20 -- .047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.17 0.27 .007 .011
c 0.09 0.20 .0035 .008
D
E
E1 6.00 6.20 .236 .244
e
L 0.45 0.75 .018 .030
N
a0°8°0°8°
aaa -- 0.10 -- .004
VARIATIONS
MIN MAX MIN MAX
56 13.90 14.10 .547 .555
10-0039
N
D mm. D (inch)
Reference Doc.: JEDEC Publicat ion 95, M O-153
0.50 BASIC 0.020 BASIC
SEE VARIATIONS SEE VARIATIONS
SEE VARIATIONS SEE VARIATIONS
8.10 BASIC 0.319 BASIC
56-Lead 6.10 mm. Bod
y
, 0.50 mm. Pitch TSSOP
(
240 mil
)
(
20 mil
)
SYMBOL
In Millimeters In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
Ordering Information
952601yGLFT
Example:
Designation for tape and reel packaging
Annealed Lead Free (optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
XXXX y G LF T
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

952601EGLF

Mfr. #:
Buy 952601EGLF
Manufacturer:
IDT
Description:
Clock Generators & Support Products PC MAIN CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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