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LTC6269IDD#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
LTC6268/LTC6269
13
62689f
For more information www.linear.com/LTC6268
R
F
contribution dominates for 10k and 100k. Since wide
band e
N
is 4.3nV/√Hz (see typical performance characterit-
ics), R
F
contribution will become a lesser factor at lower
frequencies if R
F
is less than 1.16kΩ as indicated by the
following equation:
eN/R
F
4kT /R
F
≥
1
FREQUENCY (MHz)
0
0
NOISE DENSITY (pA/√Hz)
4
3
2
1
5
60 80 10020 40
6268 F02
TOTAL
R
F
i
N
e
N
R
F
= 10k
C
IN
= 1pF
C
F
= 0.28pF
APPLICATIONS INFORMATION
Figure 2
Figure 3
Figure 4
Figure 5
FREQUENCY (Hz)
0
0
NOISE DENSITY (pA/√Hz)
4
3
2
1
5
60 80 10020 40
6268 F04
R
F
= 100k
C
IN
= 1pF
C
F
= 0.08pF
TOTAL
R
F
i
N
e
N
FREQUENCY (MHz)
0
0
NOISE DENSITY (pA/√Hz)
4
3
2
1
5
60 80 10020 40
6268 F05
R
F
= 100k
C
IN
= 5pF
C
F
= 0.18pF
TOTAL
R
F
i
N
e
N
R
F
= 10k
C
IN
= 5pF
C
F
= 0.56pF
FREQUENCY (MHz)
0
0
NOISE DENSITY (pA/√Hz)
4
3
2
1
5
60 80 10020 40
6268 F03
TOTAL
R
F
i
N
e
N
Optimizing the Bandwidth for TIA Application
The capacitance at the inverting input node can cause
amplifier stability problems if left unchecked. When the
feedback around the op amp is resistive (R
F
), a pole will
be created with R
F
||C
IN
. This pole can create excessive
phase shift and possibly oscillation. Referring to Figure
1, the response at the output is:
R
F
1+
2ζs
ω
+
S
2
ω
2
LTC6268/LTC6269
14
62689f
For more information www.linear.com/LTC6268
APPLICATIONS INFORMATION
Where R
F
is the DC gain of the TIA, ω is the natural fre-
quency of the closed loop, which can be expressed as:
ω =
2πGBW
R
F
(C
IN
+ C
F
)
ζ
is the damping factor of the loop, which can be ex-
pressed as
ζ=
1
2
1
2πGBW •R
F
(C
IN
+ C
F
)
⎛
⎝
⎜
+ R
F
C
F
+
C
IN
+ C
F
1+ A
O
⎛
⎝
⎜
⎞
⎠
⎟
+
2πGBW
R
F
C
IN
+ C
F
( )
⎞
⎠
⎟
Where C
IN
is the total capacitance at the inverting input
node of the op amp, and GBW is the gain bandwidth of
the op amp. There are two regions that the system will be
stable regardless of C
F
. The first region is when R
F
is less
than 1/(4π∙C
IN
∙GBW). In this region, the pole produced
by the feedback resistor and C
IN
is at a high frequency
which does not cause stability problems. The second
region is where:
R
F
>
A
O
2
πGBW •C
Where A
O
is the DC open loop gain of the op amp, and the
pole formed by R
F
C
IN
is the dominant pole.
For R
F
between these two regions, the small capacitor
C
F
in parallel with R
F
can introduce enough damping to
stabilize the loop. By assuming C
IN
>> C
F
, the following
condition needs to be met for C
F
,
C
F
>
C
IN
π •GBW •R
F
The above condition implies that higher GBW will require
lower
feedback capacitance C
F
, which will have higher loop
bandwidth. Table 1 shows the optimal C
F
for R
F
of 10kΩ
and 100kΩ and C
IN
of 1pF and 5pF.
Table 1. Min C
F
R
F
C
IN
= 1pF C
IN
= 5pF
10kΩ 0.25pF 0.56pF
100kΩ 0.08pF 0.18pF
Achieving Higher Bandwidth with Higher Gain TIAs
Good layout practices are essential to achieving best re
-
sults from a TIA circuit. The following two examples show
drastically
different results from an LTC6268 in a 499kΩ
TIA. (See Figure 6.) The first example is with an 0603 re
-
sistor in a basic circuit layout. In a simple layout, without
expending a lot of effort to reduce feedback capacitance,
the bandwidth achieved is about 2.5MHz. In this case,
the bandwidth of the TIA is limited not by the GBW of the
LTC6268, but rather by the fact that the feedback capaci
-
tance is
reducing the actual feedback impedance (the TIA
gain
itself) of the TIA. Basically, it’s a resistor bandwidth
limitation. The impedance of the 499kΩ is being reduced
by its own parasitic capacitance at high frequency. From
the 2.5MHz bandwidth and the 499kΩ low frequency
gain, we can estimate the total feedback capacitance as
C = 1/(2π • 2.5MHz • 499kΩ) = 0.13pF. That’s fairly low,
but it can be reduced further.
Figure 6. LTC6268 and Low Capacitance Photodiode in a 499kΩ TIA
PARASITIC
FEEDBACK C
499k
–2.5
6268 F06
K
A
PD
CASE
–2.5
PD: OSI FCI-125G-006
+2.5
I
PD
V
OUT
+
–
LTC6268
LTC6268/LTC6269
15
62689f
For more information www.linear.com/LTC6268
With some extra layout techniques to reduce feedback
capacitance, the bandwidth can be increased. Note that
we are increasing the effective “bandwidth” of the 499kΩ
resistance. One of the main ways to reduce capacitance is
to increase the distance between the plates, in this case the
plates being the two endcaps of the component resistor.
For that reason, it will serve our purposes to go to a longer
resistor. An 0805 is longer than an 0603, but its endcaps are
also larger in area, increasing capacitance again. However,
increasing distance between the endcaps is not the only way
to decrease capacitance, and the extra distance between
the resistor endcaps also allows the easy application of
another technique to reduce feedback capacitance. A very
powerful method to reduce plate to plate capacitance is to
shield the E field paths that give rise to the capacitance. In
this particular case, the method is to place a short ground
trace between the resistor pads, near the TIA output end.
APPLICATIONS INFORMATION
Figure 8. A Normal Layout at Left and a Field-Shunting Layout at Right. Simply Adding a Ground Trace Under the Feedback Resistor
Does Much to Shunt Field Away from the Feedback Side and Dumps It to Ground. Note That the Dielectric Constant of Fr4 and Ceramic
Is Typically 4, so Most of the Capacitance Is in the Solids and Not Through the Air. (Reduced Pad Size On Right Is Not Shown.)
CERAMIC R SUBSTRATE
RESISTIVE
ELEMENT
E FIELD ⇒ C
ENDCAP
K
A
G
–2.5
FR4
I
PD
V
OUT
+
–
LTC6268
E E
CERAMIC R SUBSTRATE
RESISTIVE
ELEMENT
EXTRA GND
TRACE UNDER
RESISTOR
TAKE E FIELD TO GND,
MUCH LOWER C
ENDCAP
6268 F08
K
A
G
–2.5
FR4
I
PD
V
OUT
+
–
LTC6268
Such a ground trace shields the output field from getting
to the summing node end of the resistor and effectively
shunts the field to ground instead. Keeping the trace close
to the output end increases the output load capacitance
very slightly. See Figure 8 for a pictorial representation.
Figure 9 shows the dramatic increase in bandwidth simply
by careful attention to low capacitance methods around
the feedback resistance. Bandwidth was raised from
2.5MHz to 11.2MHz, a factor greater than 4. Methods
implemented were two:
1) Minimal pad sizing. Check with your board assembler
for minimum acceptable pad sizing, or assemble this
resistor using other means, and
2) Shield the feedback capacitance using a ground trace
under the feedback resistor near the output side.
Figure 7. Frequency Response of 499kΩ TIA without
Extra Effort to Reduce Feedback Capacitance is 2.5MHz
Figure 9. LTC6268 in a 499kΩ TIA with extra Layout Effort
to Reduce Feedback Capacitance Achieves 11.2MHz BW
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

LTC6269IDD#TRPBF

Mfr. #:
Buy LTC6269IDD#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Operational Amplifiers - Op Amps 2x 500MHz Ultra-L Bias C FET In Op Amp
Lifecycle:
New from this manufacturer.
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