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LTC6269IDD#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
LTC6268/LTC6269
22
62689f
For more information www.linear.com/LTC6268
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MSOP (MS8E) 0213 REV K
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD
SHALL NOT EXCEED 0.254mm (.010") PER SIDE.
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.86
(.034)
REF
0.65
(.0256)
BSC
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
1 2
3
4
4.90 ±0.152
(.193 ±.006)
8
8
1
BOTTOM VIEW OF
EXPOSED PAD OPTION
7
6
5
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0.52
(.0205)
REF
1.68
(.066)
1.88
(.074)
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
1.68 ±0.102
(.066 ±.004)
1.88 ±0.102
(.074 ±.004)
0.889 ±0.127
(.035 ±.005)
RECOMMENDED SOLDER PAD LAYOUT
0.65
(.0256)
BSC
0.42 ±0.038
(.0165 ±.0015)
TYP
0.1016 ±0.0508
(.004 ±.002)
DETAIL “B”
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
0.05 REF
0.29
REF
MS8E Package
8-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1662 Rev K)
LTC6268/LTC6269
23
62689f
For more information www.linear.com/LTC6268
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.125
TYP
2.38 ±0.10
(2 SIDES)
15
106
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD) DFN REV C 0310
0.25 ±0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.70 ±0.05
3.55 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
LTC6268/LTC6269
24
62689f
For more information www.linear.com/LTC6268
LINEAR TECHNOLOGY CORPORATION 2014
LT 0914 • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com/LTC6268
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
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LTC6240/LTC6241/
LTC6242
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LTC6252/LTC6253/
LTC6254
720MHz, 3.5mA Power Efficient Rail-to-Rail I/O Op Amp 720MHz GBW, Unity Gain Stable, Low Noise
LTC6246/LTC6247/
LTC6248
180MHz, 1mA Power Efficient Rail-to-Rail I/O Op Amps 180MHz GBW, Unity Gain Stable, Low Noise
LT1818 400MHz, 2500V/µs, 9mA Single Operational Amplifier Unity Gain Stable, 6nV/√Hz Unity Gain Stable
LT6230 215MHz, Rail-to-Rail Output, 1.1nV/√Hz, 3.5mA Op Amp Family 350μV Max Offset Voltage, 3V to 12.6V Supply
LT6411 650MHz Differential ADC Driver/Dual Selectable Amplifier SR 3300V/µs, 6ns 0.1% Settling.
SAR ADC
LTC2376-18/
LTC2377-18/
LTC2378-18/
LTC2379-18
18-Bit, 250ksps to 1.6Msps, Low Power SAR ADC, 102dB SNR 18mW at 1.6Msps, 3.4μW at 250sps, –126dB THD.
LTC6268 as a High-Z Buffer Driving an LT1395 as a
Single-Ended to Differential Converter Into a 16-Bit ADC
Reconstructed Sampled Time Domain
Response of Above Circuit
A
IN
+
A
IN
–
LTC2269
1.8V
D15
D0
V
DD
1.8V
OV
DD
• • •
LTC2269 16-BIT 20 Msps ADC
6268 TA03
V
CM
10MHz
CLOCK
CLOCK
CONTROL
OUTPUT
DRIVERS
OGNDGND
16-BIT
ADC CORE
LTC6655-2.048
V
IN
V
OUT_s
V
OUT_F
GND
SHDN
V
IN
V
IN
= 2.048V
±1.7V FS
V
REF
R2
75Ω
R1
49.9Ω
R6
100Ω
R7
100Ω
R4
49.9Ω
R10
75Ω
R16
49.9Ω
R17
49.9Ω
R15
402Ω
R13
825Ω
R18
49.9Ω
R11
75Ω
R8
200Ω
L4
100nH
L3
100nH
C5
.01µF
R14
402Ω
R12
825Ω
R5
49.9Ω
R9
200Ω
C2
10pF
C3
10pF
C4
100µF
C
IN
0.1µF
C4
0.1µF
L1
100nH
L2
100nH
+V
+V
R3
10M
C1
22pF
U1
+
–
LTC6268
LT1395
U2
+V
+V = 5V
–V = –5V
–V
+
–
–
+
–
+
S/H
TIME (10ns/DIV)
6268 F11
f
S
= 10Msps
f
IN
= 10.101MHz
0
ADC OUTPUTS (COUNTS)
60k
52k
56k
36k
44k
48k
40k
4k
8k
12k
16k
20k
24k
28k
32k
64k
440 460 480 520 540 560 580500
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

LTC6269IDD#TRPBF

Mfr. #:
Buy LTC6269IDD#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Operational Amplifiers - Op Amps 2x 500MHz Ultra-L Bias C FET In Op Amp
Lifecycle:
New from this manufacturer.
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