INDUSTRIAL TEMPERATURE RANGE
10
IDT5T93GL101
2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER II
FSEL Operation for When Opposite Clock Dies
NOTES:
1. When the differential on the selected clock goes below the minimum DC differential, the outputs clock goes to an unknown state. When this happens, the SEL pin should be toggled
and FSEL asserted in order to force selection of the new input clock. The output clock will start up after a number of cycles of the newly-selected input clock.
2. The FSEL pin should stay asserted until the problem with the dead clock can be fixed in the system.
3. It is recommended that the FSEL be tied HIGH for systems that use only one input. If this is not possible, the user must guarantee that the unused input have a differential greater
than or equal to the minimum DC differential specified in the datasheet.
FSEL Operation for When Current Clock Dies
NOTES:
1. When the differential on the non-selected clock goes below the minimum DC differential, the outputs clock goes to an unknown state. When this happens, the FSEL pin should
be asserted in order to force selection of the new input clock. The output clock will start up after a number of cycles of the newly-selected input clock.
2. The FSEL pin should stay asserted until the problem with the dead clock can be fixed in the system.
3. It is recommended that the FSEL be tied HIGH for systems that use only one input. If this is not possible, the user must guarantee that the unused input have a differential greater
than or equal to the minimum DC differential specified in the datasheet.
