2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER II
13
Test Circuit for DC Outputs and Power Down Tests
Test Circuit for Propagation, Skew, and Gate Enable/Disable Timing
NOTES:
1. Specifications only apply to "Normal Operations" test condition. The TIA/EIA specification load is for reference only.
2.The scope inputs are assumed to have a 2pF load to ground. TIA/EIA - 644 specifies 5pF between the output pair. With CL = 8pF, this gives the test circuit appropriate 5pF equivalent
load.
LVDS OUTPUT TEST CONDITION
SymbolVDD = 2.5V ± 0.2VUnit
C
L0
(1)
pF
8
(1,2)
RL50Ω
VDD
D.U.T.
A
A
Qn
Qn
Pulse
Generator
RL
RL
VOSVOD
VDD/2
D.U.T.
A
A
Qn
Qn
Pulse
Generator
50Ω
50Ω
Z=50Ω
Z=50Ω
SCOPE
C
L
-VDD/2
CL
INDUSTRIAL TEMPERATURE RANGE
14
IDT5T93GL101
2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER II
ORDERING INFORMATION
CORPORATE HEADQUARTERSfor SALES:for Tech Support:
6024 Silver Creek Valley Road800-345-7015 or 408-284-8200clockhelp@idt.com
