INDUSTRIAL TEMPERATURE RANGE
IDT5T93GL101
2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER II
7
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
(1,5)
Symbol Parameter Min. Typ. Max Unit
Skew Parameters
tSK(O) Same Device Output Pin-to-Pin Skew
(2)
75 ps
tSK(P) Pulse Skew
(3)
——100 ps
t
SK(PP) Part-to-Part Skew
(4)
——300 ps
Propagation Delay
t
PLH Propagation Delay A, A Crosspoint to Qn, Qn Crosspoint 1.5 2.2 ns
tPHL
fO Frequency Range
(6)
——450 M Hz
Output Gate Enable/Disable Delay
tPGE Output Gate Enable Crossing VTHI to Qn/Qn Crosspoint ——3.5 ns
t
PGD Output Gate Disable Crossing VTHI to Qn/Qn Crosspoint Driven to GL Designated Level ——3.5 ns
Power Down Timing
tPWRDN PD Crossing VTHI to Qn = VDD, Qn = VDD ——100 μS
t
PWRUP Output Gate Disable Crossing VTHI to Qn/Qn Driven to GL Designated Level ——100 μS
NOTES:
1. AC propagation measurements should not be taken within the first 100 cycles of startup.
2. Skew measured between crosspoints of all differential output pairs under identical input and output interfaces, transitions and load conditions on any one device.
3. Skew measured is the difference between propagation delay times tPHL and tPLH of any single differential output pair under identical input and output interfaces, transitions and load
conditions on any one device.
4. Skew measured is the magnitude of the difference in propagation times between any single differential output pair of two devices, given identical transitions and load conditions
at identical VDD levels and temperature.
5. All parameters are tested with a 50% input duty cycle.
6. Guaranteed by design but not production tested.
INDUSTRIAL TEMPERATURE RANGE
8
IDT5T93GL101
2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER II
NOTES:
1. Pulse skew is calculated using the following expression:
tSK(P) = | tPHL - tPLH |
Note that the tPHL and tPLH shown above are not valid measurements for this calculation because they are not taken from the same pulse.
2. AC propagation measurements should not be taken within the first 100 cycles of startup.
DIFFERENTIAL AC TIMING WAVEFORMS
Output Propagation and Skew Waveforms
tPLH
tPHL
tSK(O)
tSK(O)
Qn - Qn
Qm - Qm
+VDIF
VDIF =0
-V
DIF
+VDIF
VDIF =0
-V
DIF
A[1:2] -A[1:2]
+VDIF
VDIF =0
-V
DIF
1/fo
INDUSTRIAL TEMPERATURE RANGE
IDT5T93GL101
2.5V LVDS 1:10 GLITCHLESS CLOCK BUFFER TERABUFFER II
9
Differential Gate Disable/Enable Showing Runt Pulse Generation
NOTE:
1. As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time their Gx signals to avoid this problem.
Glitchless Output Operation with Switching Input Clock Selection
NOTES:
1. When SEL changes, the output clock goes LOW on the falling edge of the output clock up to three cycles later. The output then stays LOW for up to three clock cycles of the
new input clock. After this, the output starts with the rising edge of the new input clock.
2. AC propagation measurements should not be taken within the first 100 cycles of startup.
A1 -A1
A2 -A2
SEL
Qn - Qn
+VDIF
VDIF =0
-V
DIF
+VDIF
VDIF =0
-V
DIF
VIH
VTHI
VIL
+VDIF
VDIF =0
-V
DIF
tPLH
GL
Gx
Qn - Qn
tPGD
tPGE
VIH
VTHI
VIL
VIH
VTHI
VIL
+VDIF
VDIF =0
-V
DIF
A[1:2] -A[1:2]
+VDIF
VDIF =0
-V
DIF

5T93GL101PFGI8

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 450 MHz 2.5V LVDS 1:10 Clock
Lifecycle:
New from this manufacturer.
Delivery:
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