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FUSB307BMPX

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57
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Table 36. FAULTSTATMSK
Address: 15h
Reset Value: 0xB3 (Resets on POR, SW_RST and Hard Reset)
Type: Read/Write
Bit #
Name R/W/C
Size
(Bits)
Fault Status Mask Description
7 M_ALL_REGS_RESET RW 1 All Registers Reset to Default
0b: Interrupt masked
1b: Interrupt unmasked
6 Reserved R 1 Reserved: 0b
5 M_AUTO_DISCH_FAIL RW 1 Auto Discharge Fail Interrupt Mask
0b: Interrupt masked
1b: Interrupt unmasked
4 M_FORCE_DISCH_FAIL RW 1 Force Discharge Fail Interrupt Mask
0b: Interrupt Masked
1b: Interrupt Unmasked
3 Reserved R 1 Reserved: 0b
2 Reserved R 1 Reserved: 0b
1 M_VCONN_OCP RW 1 VCONN OCP Interrupt Mask
0b: Interrupt Masked
1b: Interrupt Unmasked
0 M_I2C_ERROR RW 1 I2C Interface Error Interrupt Mask
0b: Interrupt Masked
1b: Interrupt Unmasked
Table 37. STD_OUT_CFG
Address: 18h
Reset Value: 0x40
Type: Read/Write
Bit #
Name R/W/C
Size
(Bits)
Standard Outputs Configuration
7 TRI_STATE R/W 1 0b: Standard Output Control
1b: Force all outputs to tri−state
6 DEBUG_ACC R/W 1 0b: Debug Connected output is driven Low
1b: No Debug Accessory Connected output is driven High
Note: The FUSB307B ignores writes to this bit if
TCPC_CTRL.DEBUG_ACC_CTRL = 0b
5 Reserved R 1 Reserved: 0b
4 Reserved R 1 Reserved: 0b
3:2 MUX_CTRL R/W 2 Controls MUX_S0 and MUX_S1 Outputs.
00b: MUX_S0 = 0, MUX_S1 = 0. No connection.
01b: MUX_S0 = 1, MUX_S1 = 0. USB3.1 Connected
10b: MUX_S0 = 0, MUX_S1 = 1. DP Alternate Mode – 4 lanes
11b: MUX_S0 = 1, MUX_S1 = 1. USB3.1 + Display Port Lanes 0 & 1
1 Reserved R 1 Reserved: 0b
0 ORIENT R/W 1 Controls ORIENT Output
0b: Normal (CC1 = A5, CC2 = B5, TX1 = A2/A3, RX1 = B10/B11)
1b: Flipped (CC2 = A5, CC1 = B5, TX1 = B2/B3, RX1 = A10/A11)
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38
Table 38. TCPC_CTRL
Address: 19h
Reset Value: 0x00 (POR, and SW_RST)
Type: Read/Write
Bit #
Name R/W/C Size (Bits) TCPC Control Register
7:4 Reserved R 2 Reserved: 00b
5
EN_WATCHDOG R/W 1
0b: Watchdog Monitoring is disabled (default)
1b: Watchdog Monitoring is enabled
4 DEBUG_ACC_CTRL R/W 1 Debug Accessory Control
0b: Standard Output is Controlled by FUSB307B
1b: Standard Output is Controlled by external processor
Note: See: Debug Accessory State Machine
3:2 I2C_CLK_STRETCH R 2 00b: I2C clock stretching is disabled. Writing to these register bits
will be ignored.
1 BIST_TMODE R/W 1 BIST Test Data Receive Enable
0b: Normal Operation. Incoming messages are stored and passed
to host
1b: BIST Test Mode. Receive buffer is cleared immediately after
GoodCRC response.
0 ORIENT R/W 1 Plug Orientation
0b: When Vconn is enabled, apply it to the CC2 pin. Monitor the
CC1 pin for BMC communications if PD messaging is enabled.
1b: When Vconn is enabled, apply it to the CC1 pin. Monitor the
CC2 pin for BMC communications if PD messaging is enabled.
Table 39. ROLECTRL
Address: 1Ah
Reset Value (Note 19) 0x0A for FUSB307B Device in dead battery, 0x4A for non−dead−battery.
Type: Read/Write
Bit #
Name R/W/C Size (Bits) Role Control Description
7 Reserved R 1 Reserved: 0b
6 DRP
(Notes 21, 22)
R/W 1 0b: No DRP.
Bits B3..0 determine Rp/Rd/Ra settings
1b: DRP
5:4 RP_VAL R/W 2 00b: Rp default
01b: Rp 1.5 A
10b: Rp 3.0 A
11b: Reserved
3:2 CC2_TERM
(Notes 23, 24)
R/W 2 00b: Ra
01b: Rp (Use Rp definition in B5..4)
10b: Rd
11b: Open (Disconnect or don’t care)
1:0 CC1_TERM
(Notes 23, 24)
R/W 2 00b: Ra
01b: Rp (Use Rp definition in B5..4)
10b: Rd
11b: Open (Disconnect or don’t care)
20.Reset values are loaded on either VBUS or VDD power up. Dead battery Reset values loaded on VBUS power up will be maintained when
battery is eventually present.
21.Rp value is defined in B5..4 when performing the DRP toggling as well as when a connection is resolved.
22.The FUSB307B toggles CC1 & CC2 after receiving a.LOOK4CON and until a connection is detected. Upon connection, the FUSB307B
resolves to either an Rp or Rd and report the CC1/CC2 State in the CCSTAT register. The FUSB307B will continue to present the resolved
Rd or Rp regardless of any changes voltage on the CC wires.
23.When CCx_TERM bits are set to Open and DRP = 0, the PHY and CC comparators will power down.
24.If DRP = 1, LOOK4CON starts toggling with the value set in CC1_TERM/CC2_TERM. If CC1_TERM/CC2_TERM is different than Rp/Rp
or Rd/Rd, the COMMAND will be ignored.
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Table 40. FAULTCTRL
Address: 1Bh
Reset Value: 0x00
Type: Read/Write
Bit #
Name R/W/C Size (Bits) Fault Control Description
7:4 Reserved R 4
Reserved: 0000b
3 DISCH_TIMER_DIS R/W 1
Auto and Force VBUS Discharge Timer Enable
0b: VBUS Discharge timer is enabled
1b: VBUS Discharge timer is disabled
2 Reserved R 1
Reserved: 0b
1 Reserved R 1
Reserved: 0b
0 VCONN_OCP_DIS R/W 1
VCONN OCP Enable
0b: VCONN OCP Enabled
1b: VCONN OCP Disabled
Table 41. PWRCTRL
Address: 1Ch
Reset Value: 0x60
Type: Read/Write
Bit #
Name R/W/C Size (Bits) Power Control Description
7 Reserved R 1 Reserved: 0b
6
DIS_VBUS_MON
(Note 25)
R/W 1
Controls VBUS_VOLTAGE_L Monitoring.
0b: VBUS Voltage Monitoring is enabled
1b: VBUS Voltage Monitoring is disabled
5
DIS_VALARM R/W 1
Disables VALARMHCFGL and VALARMLCFGL
0b: Voltage Alarm reporting is enabled
1b:Voltage Alarm reporting is disabled
4
AUTO_DISCH
(Notes 26, 28)
R/W 1
Auto Discharge on Disconnect
0b: Turn Off Automatically Discharge VBUS based on VBUS Voltage
1b: Turn On Automatically Discharge VBUS based on VBUS Voltage
3
EN_BLEED_DISCH
(Note 30)
R/W 1
Enable Bleed Discharge
0b: Disable bleed discharge of VBUS
1b: Enable bleed discharge of V
BUS
2
FORCE_DISCH
(Note 27, 29)
R/W 1
Force Discharge
0b: Disable forced discharge of VBUS
1b: Enable forced discharge of VBUS
1
VCONN_PWR R/W 1
VCONN Power Supported
Writing this bit has no function. Please use VCONN_OCP to set
OCP values
0
EN_VCONN R/W 1
Enable VCONN
0b: Disable V
CONN Source (default)
1b: Enable VCONN Source to CC
25.If VBUS_MON is disabled, VBUS_VOLTAGE_L and VBUS_VOLTAGE_H reports all zeroes.
26.Setting this bit in a Source FUSB307B triggers the following actions upon disconnection detection:
1. Disable sourcing power over Vbus
2. VBUS discharge
27.Sourcing power over Vbus shall be disabled before or at same time as starting VBUS discharge.
28.Setting this bit in a Sink FUSB307B triggers the following action upon disconnection detection:
1. VBUS discharge
29.The FUSB307B will automatically disable discharge once the voltage on VBUS is below vSafe0V (max.).
30.Bleed Discharge is a low current discharge to provide a minimum load current if needed.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57

FUSB307BMPX

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Buy FUSB307BMPX
Manufacturer:
ON Semiconductor
Description:
USB Interface IC USB-C TCPC PORT CONT
Lifecycle:
New from this manufacturer.
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